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1. 发明申请

US20200076805A1 INFORMATION PROCESSING APPARATUS, SYSTEM AND METHOD 审中-公开
公开(公告)号：US20200076805A1
公开(公告)日：2020-03-05
申请号：US16270186
申请日：2019-02-07
申请人： Kabushiki Kaisha Toshiba , Toshiba Electronic Devices & Storage Corporation
发明人： Ryuiti Koike , Mikio Hashimoto , Atsushi Shimbo
IPC分类号： H04L29/06 , G06F11/36 , H04L9/32 , G06F21/12
摘要： According to one embodiment, an information processing apparatus is applied to an embedded system in an electric device and includes a first circuit. The first circuit is configured to request a server different from the information processing apparatus to determine whether a debug or software change is possible in response to external access.

2. 发明授权

US09460316B2 Authentication device, authentication method, and computer program product 有权
标题翻译：认证设备，认证方法和计算机程序产品
公开(公告)号：US09460316B2
公开(公告)日：2016-10-04
申请号：US14190463
申请日：2014-02-26
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Tetsufumi Tanamoto , Takao Marukame , Shinichi Yasuda , Yuichiro Mitani , Atsushi Shimbo , Tatsuya Kishi
IPC分类号： G06F12/14 , G06F21/73 , G11C11/16 , G11C13/00 , G11C16/10 , G11C16/34 , G11C7/24
CPC分类号： G06F21/73 , G11C7/24 , G11C11/16 , G11C11/161 , G11C11/1675 , G11C13/0035 , G11C16/10 , G11C16/349
摘要： According to an embodiment, an authentication device includes an acquiring unit, a predicting unit, and an authenticating unit. The acquiring unit is configured to acquire performance information of a first device that is a device to be authenticated. The predicting unit is configured to predict performance information of a second device that is a device being a reference for authentication according to a change with time from initial performance information. The authenticating unit is configured to perform an authentication process of determining whether or not the first device falls into the second device on a basis of a degree of agreement between the performance information acquired by the acquiring unit and the performance information predicted by the predicting unit.
摘要翻译：根据实施例，认证装置包括获取单元，预测单元和认证单元。获取单元被配置为获取作为要认证的设备的第一设备的性能信息。预测单元被配置为根据与初始性能信息随时间的变化来预测作为用于认证的参考的设备的第二设备的性能信息。认证单元被配置为基于由获取单元获取的演奏信息与由预测单元预测的演奏信息之间的一致性来执行确定第一设备是否落入第二设备的认证处理。

3. 发明授权

US09053062B2 Memory chip for converting data received from controller controlling reading and writing of data 有权
标题翻译：用于转换从控制数据读取和写入的控制器接收的数据的存储器芯片
公开(公告)号：US09053062B2
公开(公告)日：2015-06-09
申请号：US14303704
申请日：2014-06-13
申请人： Kabushiki Kaisha Toshiba
发明人： Toru Kambayashi , Akihiro Kasahara , Shinichi Matsukawa , Hiroyuki Sakamoto , Taku Kato , Hiroshi Sukegawa , Yoshihiko Hirose , Atsushi Shimbo , Koichi Fujisaki
IPC分类号： G11C29/00 , G06F12/14 , G06F21/79 , H04L9/08 , G06F21/30
CPC分类号： G06F12/1466 , G06F21/30 , G06F21/79 , G06F2212/1052 , G06F2221/2107 , H04L9/08 , H04L9/0838 , H04L9/0897 , H04L2209/34 , H04L2463/062
摘要： According to one embodiment, a memory chip, which is connected to a controller that controls reading and writing of data in response to a request from an external device, includes: a memory including a special area that is a predetermined data storage area; a key storage unit that stores therein a second key that corresponds to a first key used by the external device to convert the data; a converting unit that receives, from the controller, data to be written into the special area and generates converted data by converting the data to be written using the second key; and a writing unit that writes the converted data into the special area.
摘要翻译：根据一个实施例，连接到控制器的存储器芯片，其响应于来自外部设备的请求来控制数据的读取和写入，包括：存储器，包括作为预定数据存储区域的特殊区域; 密钥存储单元，其中存储与由外部设备用于转换数据的第一密钥相对应的第二密钥; 从所述控制器接收要写入所述特殊区域的数据并通过使用所述第二密钥转换要写入的数据来生成转换数据的转换单元; 以及将转换的数据写入特殊区域的写入单元。

4. 发明申请

US20130290738A1 MEMORY CHIP 有权
公开(公告)号：US20130290738A1
公开(公告)日：2013-10-31
申请号：US13924675
申请日：2013-06-24
申请人： Kabushiki Kaisha Toshiba
发明人： Toru KAMBAYASHI , Akihiro Kasahara , Shinichi Matsukawa , Hiroyuki Sakamoto , Taku Kato , Hiroshi Sukegawa , Yoshihiko Hirose , Atsushi Shimbo , Koichi Fujisaki
IPC分类号： G06F21/79
CPC分类号： G06F12/1466 , G06F21/30 , G06F21/79 , G06F2212/1052 , G06F2221/2107 , H04L9/08 , H04L9/0838 , H04L9/0897 , H04L2209/34 , H04L2463/062
摘要： According to one embodiment, a memory chip, which is connected to a controller that controls reading and writing of data in response to a request from an external device, includes: a memory including a special area that is a predetermined data storage area; a key storage unit that stores therein a second key that corresponds to a first key used by the external device to convert the data; a converting unit that receives, from the controller, data to be written into the special area and generates converted data by converting the data to be written using the second key; and a writing unit that writes the converted data into the special area.

5. 发明授权

US08543630B2 Exponentiation calculation apparatus and method for calculating square root in finite extension field 有权
标题翻译：指数计算装置和有限扩展场中平方根的计算方法
公开(公告)号：US08543630B2
公开(公告)日：2013-09-24
申请号：US13854554
申请日：2013-04-01
申请人： Kabushiki Kaisha Toshiba
发明人： Tomoko Yonemura , Hirofumi Muratani , Atsushi Shimbo , Kenji Ohkuma , Taichi Isogai , Yuichi Komano , Kenichiro Furuta , Yoshikazu Hanatani
IPC分类号： G06F17/10 , G06F7/38 , G06F7/52 , G06F7/50 , H04L9/28
CPC分类号： G06F17/10 , G06F7/724
摘要： In a computing device that calculates a square of an element in a finite field, a vector representation of the element in the finite field is accepted. The vector representation includes a plurality of elements. The computing device performs a multiplication operation on a base field using the accepted elements, and obtains a multiplication value. The multiplication operation is determined by a condition under which the element in the finite field is placed in an algebraic torus. The computing device performs an addition and subtraction operation using the obtained multiplication value and the accepted elements, and obtains a calculation result of the square of the element. The addition and subtraction operation is determined by the condition. The computing device then outputs the calculation result.
摘要翻译：在计算有限域中的元素的平方的计算设备中，接受有限域中元素的向量表示。向量表示包括多个元素。计算装置使用接受的元素对基地区进行乘法运算，得到乘法值。乘法运算由有限域内的元素置于代数圆环中的条件决定。计算装置使用所获得的乘法值和可接受的元素进行加减运算，并获得元素的平方的计算结果。加法和减法操作由条件确定。计算装置然后输出计算结果。

6. 发明申请

US20130218939A1 EXPONENTIATION CALCULATION APPARATUS AND METHOD FOR CALCULATING SQUARE ROOT IN FINITE EXTENSION FIELD 有权
标题翻译：有限扩展场计算方法的计算方法及计算方法
公开(公告)号：US20130218939A1
公开(公告)日：2013-08-22
申请号：US13854554
申请日：2013-04-01
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Tomoko YONEMURA , Hirofumi Muratani , Atsushi Shimbo , Kenji Ohkuma , Taichi Isogai , Yuichi Komano , Kenichiro Furuta , Yoshikazu Hanatani
IPC分类号： G06F17/10
CPC分类号： G06F17/10 , G06F7/724
摘要： In a computing device that calculates a square of an element in a finite field, a vector representation of the element in the finite field is accepted. The vector representation includes a plurality of elements. The computing device performs a multiplication operation on a base field using the accepted elements, and obtains a multiplication value. The multiplication operation is determined by a condition under which the element in the finite field is placed in an algebraic torus. The computing device performs an addition and subtraction operation using the obtained multiplication value and the accepted elements, and obtains a calculation result of the square of the element. The addition and subtraction operation is determined by the condition. The computing device then outputs the calculation result.
摘要翻译：在计算有限域中的元素的平方的计算设备中，接受有限域中元素的向量表示。向量表示包括多个元素。计算装置使用接受的元素对基地区进行乘法运算，得到乘法值。乘法运算由有限域内的元素置于代数圆环中的条件决定。计算装置使用所获得的乘法值和可接受的元素进行加减运算，并获得元素的平方的计算结果。加法和减法操作由条件确定。计算装置然后输出计算结果。

7. 发明授权

US11546148B2 Information processing device, information processing system, and method for controlling information processing device including comparing request order information and order comparison information 有权
公开(公告)号：US11546148B2
公开(公告)日：2023-01-03
申请号：US16883065
申请日：2020-05-26
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
发明人： Mikio Hashimoto , Atsushi Shimbo
IPC分类号： H04L9/08 , H04L9/40
摘要： An information processing device updates its own secret key according to an update request including request order information, the information processing device being provided with: a storage unit that stores, in a nonvolatile manner, a master secret key, a secret key, and order comparison information that enables comparison of the request order of the update request; and an update unit that, in a case where the update request has been made, compares the request order information and the order comparison information, and in a case where it has been determined that the order of the update request is authorized, updates the order comparison information to information corresponding to the request order information before update processing of the secret key is performed by using the master secret key.

8. 发明授权

US08788907B2 Memory chip for converting data received from controller controlling reading and writing of data 有权
标题翻译：用于转换从控制数据读取和写入的控制器接收的数据的存储器芯片
公开(公告)号：US08788907B2
公开(公告)日：2014-07-22
申请号：US13924675
申请日：2013-06-24
申请人： Kabushiki Kaisha Toshiba
发明人： Toru Kambayashi , Akihiro Kasahara , Shinichi Matsukawa , Hiroyuki Sakamoto , Taku Kato , Hiroshi Sukegawa , Yoshihiko Hirose , Atsushi Shimbo , Koichi Fujisaki
IPC分类号： H03M13/00 , G06F21/30 , H04L9/08
CPC分类号： G06F12/1466 , G06F21/30 , G06F21/79 , G06F2212/1052 , G06F2221/2107 , H04L9/08 , H04L9/0838 , H04L9/0897 , H04L2209/34 , H04L2463/062
摘要： According to one embodiment, a memory chip, which is connected to a controller that controls reading and writing of data in response to a request from an external device, includes: a memory including a special area that is a predetermined data storage area; a key storage unit that stores therein a second key that corresponds to a first key used by the external device to convert the data; a converting unit that receives, from the controller, data to be written into the special area and generates converted data by converting the data to be written using the second key; and a writing unit that writes the converted data into the special area.
摘要翻译：根据一个实施例，连接到控制器的存储器芯片，其响应于来自外部设备的请求来控制数据的读取和写入，包括：存储器，包括作为预定数据存储区域的特殊区域; 密钥存储单元，其中存储与由外部设备用于转换数据的第一密钥相对应的第二密钥; 从所述控制器接收要写入所述特殊区域的数据并通过使用所述第二密钥转换要写入的数据来生成转换数据的转换单元; 以及将转换的数据写入特殊区域的写入单元。

9. 发明授权

US09547475B2 Random number generating circuit 有权
标题翻译：随机数发生电路
公开(公告)号：US09547475B2
公开(公告)日：2017-01-17
申请号：US14086389
申请日：2013-11-21
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Shinichi Yasuda , Tetsufumi Tanamoto , Noriko Inoue , Akira Tomita , Ryusuke Murakami , Atsushi Shimbo
IPC分类号： G06F7/58
CPC分类号： G06F7/588 , G06F7/58 , G06F7/582 , G06F7/584
摘要： According to one embodiment, a random number generating circuit includes first to N-th oscillating circuits (N is a natural number equal to 2 or greater), first to N-th latch circuits that latch outputs of the first to N-th oscillating circuits by a first clock having a first frequency, first to N-th exclusive OR circuits, (N+1)-th to (2×N)-th latch circuits that latch outputs of the first to N-th exclusive OR circuits by the first clock, an (N+1)-th exclusive OR circuit that outputs an exclusive OR of outputs of the (N+1)-th to (2×N)-th latch circuits, and an M-bit shift register that converts serial data output from the (N+1)-th exclusive OR circuit into M-bit parallel data (M is a natural number equal to 2 or greater) by a second clock having a second frequency.
摘要翻译：根据一个实施例，随机数产生电路包括第一至第N振荡电路（N为等于2或更大的自然数），锁存第一至第N振荡电路的第一至第N锁存电路通过具有第一频率，第一至第N异或电路的第一时钟，（N + 1）至第（2×N）个锁存电路，其锁存第一至第N异或电路的输出第一时钟，输出第（N + 1）〜（2×N）个锁存电路的输出的异或的第（N + 1）异或电路，以及M位移位寄存器，通过具有第二频率的第二时钟从第（N + 1）异或电路输出到M位并行数据（M为等于2或更大的自然数）的串行数据。

10. 发明授权

US09355045B2 Memory device for converting data received from controller controlling reading and writing of data 有权
标题翻译：用于转换从控制数据读取和写入的控制器接收的数据的存储器件
公开(公告)号：US09355045B2
公开(公告)日：2016-05-31
申请号：US14700385
申请日：2015-04-30
申请人： Kabushiki Kaisha Toshiba
发明人： Toru Kambayashi , Akihiro Kasahara , Shinichi Matsukawa , Hiroyuki Sakamoto , Taku Kato , Hiroshi Sukegawa , Yoshihiko Hirose , Atsushi Shimbo , Koichi Fujisaki
IPC分类号： G11C29/00 , G06F12/14 , G06F21/30 , H04L9/08
CPC分类号： G06F12/1466 , G06F21/30 , G06F21/79 , G06F2212/1052 , G06F2221/2107 , H04L9/08 , H04L9/0838 , H04L9/0897 , H04L2209/34 , H04L2463/062
摘要： According to one embodiment, a memory chip, which is connected to a controller that controls reading and writing of data in response to a request from an external device, includes: a memory including a special area that is a predetermined data storage area; a key storage unit that stores therein a second key that corresponds to a first key used by the external device to convert the data; a converting unit that receives, from the controller, data to be written into the special area and generates converted data by converting the data to be written using the second key; and a writing unit that writes the converted data into the special area.
摘要翻译：根据一个实施例，连接到控制器的存储器芯片，其响应于来自外部设备的请求来控制数据的读取和写入，包括：存储器，包括作为预定数据存储区域的特殊区域; 密钥存储单元，其中存储与由外部设备用于转换数据的第一密钥相对应的第二密钥; 从所述控制器接收要写入所述特殊区域的数据并通过使用所述第二密钥转换要写入的数据来生成转换数据的转换单元; 以及将转换的数据写入特殊区域的写入单元。

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