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1. 发明授权

US09570181B2 Memory system 有权
标题翻译：内存系统
公开(公告)号：US09570181B2
公开(公告)日：2017-02-14
申请号：US15058828
申请日：2016-03-02
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Takao Marukame , Kazuya Matsuzawa , Yoshifumi Nishi , Jiezhi Chen , Yusuke Higashi , Yuuichiro Mitani
IPC分类号： G11C16/14 , G11C16/10 , G11C16/06 , G11C16/04 , G11C11/56 , G11C16/08 , G11C16/26 , G11C13/00
CPC分类号： G11C16/10 , G11C11/5628 , G11C11/5642 , G11C13/0002 , G11C13/0023 , G11C13/004 , G11C13/0069 , G11C16/0408 , G11C16/0483 , G11C16/06 , G11C16/08 , G11C16/26 , G11C2213/72 , G11C2213/77
摘要： According to an embodiment, a memory system includes first wiring lines; second wiring lines; third wiring lines; fourth wiring lines; and first and second storages. The first storage includes first memory cells arranged at intersections of the first wiring lines and the second wiring lines. Each of the third wiring lines is connected to any one of the first wiring lines. Each of the fourth wiring lines is pre-associated with a logical address specified by a host apparatus. The second storage includes second memory cells arranged at intersections of the third wiring lines and the fourth wiring lines. A resistance state of each of the second memory cells is set to a first resistance state or a second resistance state where a resistance value is lower than that in the first resistance state, according to a correspondence relationship between the logical address and the first wiring line.
摘要翻译：根据实施例，存储器系统包括第一布线; 第二布线; 第三条布线; 第四条接线; 第一和第二存储。第一存储器包括布置在第一布线和第二布线的交点处的第一存储单元。每个第三布线连接到第一布线中的任一个。第四布线中的每一条与由主机设备指定的逻辑地址预先关联。第二存储器包括布置在第三布线和第四布线的交叉处的第二存储单元。根据逻辑地址和第一布线之间的对应关系，将第二存储单元中的每一个的电阻状态设置为第一电阻状态或电阻值低于第一电阻状态的第二电阻状态。

2. 发明授权

US09164704B2 Semiconductor storage device for handling write to nonvolatile memories with data smaller than a threshold 有权
标题翻译：半导体存储装置，用于处理写入数据小于阈值的非易失性存储器
公开(公告)号：US09164704B2
公开(公告)日：2015-10-20
申请号：US14090597
申请日：2013-11-26
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Takao Marukame , Takahiro Kurita , Yuki Sasaki , Jiezhi Chen , Yusuke Higashi , Yuichiro Mitani
IPC分类号： G06F12/10 , G06F3/06 , G06F12/02
CPC分类号： G06F3/061 , G06F3/0655 , G06F3/0656 , G06F3/0679 , G06F3/0688 , G06F12/0246 , G06F12/0292 , G06F2212/7201
摘要： According to an embodiment, a semiconductor storage device includes a first storage unit, a read control unit, a second storage unit, and a write control unit. The first storage unit is configured to store data supplied from a host device. The read control unit is configured to perform control of reading the data in accordance with a read request. The second storage unit is configured to store a logical address used for reading the data from the first storage unit by the read control unit. The write control unit is configured to perform control of adding the stored logical address to the data and write the resulting data into the first storage unit in a case where a size of the data requested to be written into the first storage unit by the host device is smaller than a threshold.
摘要翻译：根据实施例，半导体存储装置包括第一存储单元，读取控制单元，第二存储单元和写入控制单元。第一存储单元被配置为存储从主机设备提供的数据。读取控制单元被配置为执行根据读取请求读取数据的控制。第二存储单元被配置为存储用于由读取控制单元从第一存储单元读取数据的逻辑地址。写入控制单元被配置为执行将所存储的逻辑地址与数据相加的控制，并且在由主机设备请求写入第一存储单元的数据的大小的情况下，将得到的数据写入第一存储单元小于阈值。

3. 发明授权

US10078550B2 Memory system, error correction device, and error correction method 有权
公开(公告)号：US10078550B2
公开(公告)日：2018-09-18
申请号：US14842356
申请日：2015-09-01
申请人： Kabushiki Kaisha Toshiba
发明人： Takao Marukame , Yoshifumi Nishi , Yusuke Higashi , Jiezhi Chen , Kazuya Matsuzawa , Yuichiro Mitani
IPC分类号： G06F11/10 , G06F13/00 , G06F11/08 , H03M13/11 , H03M13/37 , H03M13/29 , H03M13/35 , H03M13/00 , H03M13/15
CPC分类号： G06F11/1076 , H03M13/1102 , H03M13/152 , H03M13/2906 , H03M13/353 , H03M13/6516
摘要： According to an embodiment, a memory system includes a memory and a computation unit. Into the memory, data are written. The memory stores therein multiple check matrices. Each of the check matrices is associated with the number of errors in the written data. The computation unit is configured to perform a first error correction on the written data by selectively using, from among the check matrices, a check matrix associated with the number of errors recognized in the written data.

4. 发明授权

US09794073B2 Information processing system and semiconductor device 有权
公开(公告)号：US09794073B2
公开(公告)日：2017-10-17
申请号：US14877394
申请日：2015-10-07
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Jiezhi Chen , Tetsufumi Tanamoto , Yuichiro Mitani
IPC分类号： G06F21/00 , H04L9/32 , G06F21/73
CPC分类号： H04L9/3278 , G06F21/73
摘要： According to an embodiment, an information processing system includes a time constant processor and a pattern generator. The time constant processor binarizes values indicating a plurality of unit circuits each including a gate insulating film on the basis of a time to emission indicating a time from when a defect in the gate insulating film captures a carrier in a channel current caused to flow by application of a gate voltage to the unit circuits to when the defect emits the carrier. The pattern generator generates a pattern unique to the unit circuits using the values indicating the respective unit circuits binarized by the time constant processor.

5. 发明申请

US20160004440A1 SEMICONDUCTOR STORAGE DEVICE 审中-公开
标题翻译：半导体存储设备
公开(公告)号：US20160004440A1
公开(公告)日：2016-01-07
申请号：US14851229
申请日：2015-09-11
申请人： Kabushiki Kaisha Toshiba
发明人： Takao Marukame , Takahiro Kurita , Yuki Sasaki , Jiezhi Chen , Yusuke Higashi , Yuichiro Mitani
IPC分类号： G06F3/06 , G06F12/02
CPC分类号： G06F3/061 , G06F3/0655 , G06F3/0656 , G06F3/0679 , G06F3/0688 , G06F12/0246 , G06F12/0292 , G06F2212/7201
摘要： According to an embodiment, a semiconductor storage device includes a first storage unit, a read control unit, a second storage unit, and a write control unit. The first storage unit is configured to store data supplied from a host device. The read control unit is configured to perform control of reading the data in accordance with a read request. The second storage unit is configured to store a logical address used for reading the data from the first storage unit by the read control unit. The write control unit is configured to perform control of adding the stored logical address to the data and write the resulting data into the first storage unit in a case where a size of the data requested to be written into the first storage unit by the host device is smaller than a threshold.
摘要翻译：根据实施例，半导体存储装置包括第一存储单元，读取控制单元，第二存储单元和写入控制单元。第一存储单元被配置为存储从主机设备提供的数据。读取控制单元被配置为执行根据读取请求读取数据的控制。第二存储单元被配置为存储用于由读取控制单元从第一存储单元读取数据的逻辑地址。写入控制单元被配置为执行将所存储的逻辑地址与数据相加的控制，并且在由主机设备请求写入第一存储单元的数据的大小的情况下，将得到的数据写入第一存储单元小于阈值。

6. 发明授权

US09665426B2 Semiconductor device and reading method 有权
公开(公告)号：US09665426B2
公开(公告)日：2017-05-30
申请号：US14945932
申请日：2015-11-19
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Jiezhi Chen , Kuniharu Takahashi , Hiroyuki Nagashima , Yuichiro Mitani , Katsuki Matsudera , Kazunori Kanebako
IPC分类号： G11C29/00 , G06F11/10 , G11C11/56 , G11C29/52 , G11C16/26 , G11C16/34 , G11C16/04 , G11C29/02 , G11C29/04
CPC分类号： G06F11/1072 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C16/3418 , G11C29/021 , G11C29/028 , G11C29/52 , G11C2029/0411
摘要： According to an embodiment, a semiconductor device includes an error corrector, a read controller, and a majority processor. The error corrector is configured to perform error correction on data read from a storage, and output the number of errors contained in the data when errors cannot be corrected by the error correction. The read controller is configured to read pieces of data from a first address in the storage according to respective read conditions, select, from the read conditions, a read condition corresponding to a smallest of the numbers of errors obtained by the error correction performed on the pieces of data corresponding to the respective read conditions, and perform reading from the first address multiple times according to the selected read condition. The majority processor is configured to perform a majority process between a plurality of pieces of data obtained by the multiple times of reading.

7. 发明授权

US09349948B2 Non-volatile variable resistive element, controlling device and storage device 有权
标题翻译：非易失性可变电阻元件，控制装置和存储装置
公开(公告)号：US09349948B2
公开(公告)日：2016-05-24
申请号：US13965733
申请日：2013-08-13
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Jiezhi Chen , Reika Ichihara , Yuuichiro Mitani
IPC分类号： G11C13/00 , H01L45/00 , H01L27/24 , G11C11/56
CPC分类号： H01L45/12 , G11C11/5685 , G11C13/0002 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C2013/0073 , G11C2213/77 , H01L27/2463 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/148 , H01L45/16
摘要： A non-volatile variable resistive element according to an embodiment comprises a first electrode including a first metal, a second electrode including a second metal, a third electrode placed opposite to the first and second electrodes, and a variable resistive layer placed between the first and second electrodes and the third electrode, a resistance of the variable resistive layer reducing when at least either one of the first metal and the second metal is diffused into the variable resistive layer and the resistance of the variable resistive layer rising when at least either one of the first metal and the second metal diffused into the variable resistive layer is collected by the first electrode or the second electrode.
摘要翻译：根据实施例的非易失性可变电阻元件包括包括第一金属的第一电极，包括第二金属的第二电极，与第一和第二电极相对设置的第三电极，以及置于第一和第二电极之间的可变电阻层第二电极和第三电极，当第一金属和第二金属中的至少一个被扩散到可变电阻层中时，可变电阻层的电阻减小，并且当可变电阻层中的至少一个扩散到可变电阻层中的第一金属和第二金属由第一电极或第二电极收集。

8. 发明授权

US09286995B2 Memory system and control method 有权
标题翻译：内存系统和控制方法
公开(公告)号：US09286995B2
公开(公告)日：2016-03-15
申请号：US14669687
申请日：2015-03-26
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Jiezhi Chen , Yuichiro Mitani
IPC分类号： G11C16/10 , G11C16/34 , G11C11/56
CPC分类号： G11C16/3427 , G11C11/5628 , G11C11/5671 , G11C16/3431 , G11C16/3459
摘要： A memory system according to embodiments comprises a memory chip that includes a memory cell array having a plurality of memory cells, a first writing unit that writes first data in a first memory cell in the memory cell array, and a second writing unit that writes second data in a second memory cell which is adjacent to the first memory cell. The second data is used in adjusting a threshold value of the first memory cell.
摘要翻译：根据实施例的存储器系统包括存储器芯片，其包括具有多个存储器单元的存储单元阵列，将第一数据写入存储单元阵列中的第一存储单元的第一写入单元和写入第二存储单元的第二写入单元与第一存储单元相邻的第二存储单元中的数据。第二数据用于调整第一存储单元的阈值。

9. 发明授权

US09424927B2 Memory system, control system and method of predicting lifetime 有权
标题翻译：存储系统，控制系统和预测寿命的方法
公开(公告)号：US09424927B2
公开(公告)日：2016-08-23
申请号：US14187668
申请日：2014-02-24
申请人： Kabushiki Kaisha Toshiba
发明人： Jiezhi Chen , Tetsufumi Tanamoto , Yuichiro Mitani , Takao Marukame
IPC分类号： G11C16/00 , G11C16/06 , G11C11/56 , G11C16/04 , G11C16/34
CPC分类号： G11C16/06 , G11C11/5628 , G11C16/0483 , G11C16/3495
摘要： A memory system according to an embodiment may have an integration unit and a prediction unit. The integration unit may detect substrate current flowing through a substrate of a non-volatile memory when the non-volatile memory with a memory cell which has binary or multivalued being the binary or more is written/erased. The integration unit may records an integration value of the detected substrate current into a storage. The prediction unit may predict a lifetime of the non-volatile memory based on the integration value which is recorded on the storage.
摘要翻译：根据实施例的存储器系统可以具有集成单元和预测单元。当具有二进制或多值的二进制或多值的存储单元的非易失性存储器被写/擦除时，积分单元可以检测流过非易失性存储器的衬底的衬底电流。积分单元可以将检测到的衬底电流的积分值记录到存储器中。预测单元可以基于记录在存储器上的积分值来预测非易失性存储器的寿命。

10. 发明授权

US09054739B2 Error correction device, error correction method and computer program product 有权
标题翻译：纠错装置，纠错方法和电脑程序产品
公开(公告)号：US09054739B2
公开(公告)日：2015-06-09
申请号：US13861547
申请日：2013-04-12
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Takao Marukame , Yoshifumi Nishi , Jiezhi Chen , Yusuke Higashi , Takahiro Kurita , Yuuichiro Mitani , Atsuhiro Kinoshita
IPC分类号： H03M13/00 , H03M13/11
CPC分类号： H03M13/1102 , H03M13/1108
摘要： According to an embodiment, an error correction device includes first calculators, second calculators, estimators, and an inverter. Each first calculator calculates a first message representing a probability that 1-bit data that is input in a corresponding variable node is 1. Each second calculator calculates a second message representing a probability that a value of the data input to the variable node is 1 for each of two or more variable nodes connected to the check node by using the first messages of the variable nodes connected to the check node. Each estimator estimates a true value of the data input to the variable node to generate an estimated value by using the first and second messages. The inverter inverts the estimated value associated with at least one of the variable nodes with a probability higher than 0 and lower than 1.
摘要翻译：根据实施例，纠错装置包括第一计算器，第二计算器，估计器和逆变器。每个第一计算器计算表示在对应的可变节点中输入的1位数据为1的概率的第一消息。每个第二计算器计算表示输入到变量节点的数据的值为1的概率的第二消息，通过使用连接到校验节点的变量节点的第一消息将两个或多个可变节点中的每一个连接到校验节点。每个估计器估计输入到变量节点的数据的真实值，以通过使用第一和第二消息来生成估计值。逆变器以概率高于0并低于1的方式来反转与至少一个变量节点相关联的估计值。

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