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1. 发明申请

US20170262334A1 MEMORY SYSTEM AND CONTROL METHOD 有权
公开(公告)号：US20170262334A1
公开(公告)日：2017-09-14
申请号：US15257336
申请日：2016-09-06
申请人： Kabushiki Kaisha Toshiba
发明人： Hironori UCHIKAWA , Kenji SAKURADA
IPC分类号： G06F11/10 , G11C16/26 , G11C29/52 , G11C16/16 , G06F3/06 , G11C16/10 , G11C11/56
CPC分类号： G11C16/04 , G06F3/064 , G06F11/1012 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/16 , G11C16/26 , G11C29/52
摘要： A memory system and method is provided. The memory system includes a non-volatile memory, a memory interface, and a code processor. The code processor generates a likelihood value for a first read bit, which is read from a first memory cell, from among read bits contained in a codeword read by the memory interface from the non-volatile memory. For example, the likelihood value can be based on the value of the first read bit and on the value of a second read bit read from a second memory cell adjacent to the first memory cell so as to decode the codeword using the generated likelihood value.

2. 发明申请

US20140019819A1 RECEIVER AND RECEIVING METHOD 审中-公开
标题翻译：接收和接收方法
公开(公告)号：US20140019819A1
公开(公告)日：2014-01-16
申请号：US13936040
申请日：2013-07-05
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Toshiyuki NAKANISHI , Hironori UCHIKAWA , Zhixiang CHEN
IPC分类号： H03M13/11
CPC分类号： H03M13/11 , H03M13/1111 , H03M13/255 , H03M13/2957 , H03M13/6325
摘要： According to an embodiment, a receiver includes a generation unit and a scheduler. The generation unit generates a convergence indicator for evaluating a convergence status of the iterative decoding process based on reliability information. The scheduler controls execution of local iteration includes the iterative decoding process terminates and controls execution of global iteration includes alternation between a symbol de-mapping process and an iterative decoding process, based on the convergence indicator.
摘要翻译：根据实施例，接收机包括生成单元和调度器。生成单元基于可靠性信息生成用于评价迭代解码处理的收敛状态的收敛指示符。调度器控制本地迭代的执行包括迭代解码过程终止并且控制全局迭代的执行包括基于收敛指示符的符号解映射处理和迭代解码处理之间的交替。

3. 发明申请

US20170141799A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME 审中-公开
公开(公告)号：US20170141799A1
公开(公告)日：2017-05-18
申请号：US15421746
申请日：2017-02-01
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Shinichi KANNO , Hironori UCHIKAWA
IPC分类号： H03M13/29 , H03M13/00 , G06F11/10 , G11C29/52 , G06F13/16 , G06F13/40
摘要： A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.

4. 发明申请

US20160034354A1 GLOBAL ERROR RECOVERY SYSTEM 审中-公开
标题翻译：全球错误恢复系统
公开(公告)号：US20160034354A1
公开(公告)日：2016-02-04
申请号：US14815789
申请日：2015-07-31
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Daisuke HASHIMOTO , Hironori UCHIKAWA
IPC分类号： G06F11/10 , G06F3/06
CPC分类号： G06F3/0683 , G06F11/108
摘要： In a network storage device that includes a plurality of data storage drives, error correction and/or recovery of data stored on one of the plurality of data storage drives is performed cooperatively by the drive itself and by a storage host that is configured to manage storage in the plurality of data storage drives. When an error-correcting code (ECC) operation performed by the drive cannot correct corrupted data stored on the drive, the storage host can attempt to correct the corrupted data based on parity and user data stored on the remaining data storage drives. In some embodiments, data correction can be performed iteratively between the drive and the storage host. Furthermore, the storage host can control latency associated with error correction by selecting a particular error correction process.
摘要翻译：在包括多个数据存储驱动器的网络存储设备中，存储在多个数据存储驱动器之一上的数据的错误校正和/或恢复由驱动器本身和被配置为管理存储器的存储主机协作地执行在多个数据存储驱动器中。当由驱动器执行的纠错码（ECC）操作不能校正存储在驱动器上的损坏的数据时，存储主机可以基于存储在剩余数据存储驱动器上的奇偶校验和用户数据来尝试校正损坏的数据。在一些实施例中，可以在驱动器和存储主机之间迭代地执行数据校正。此外，存储主机可以通过选择特定的纠错处理来控制与纠错相关联的延迟。

5. 发明申请

US20140215288A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US20140215288A1
公开(公告)日：2014-07-31
申请号：US14231140
申请日：2014-03-31
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Shinichi KANNO , Hironori UCHIKAWA
IPC分类号： G06F11/10 , H03M13/29
CPC分类号： H03M13/2906 , G06F11/10 , G06F11/1004 , G06F11/1008 , G06F11/1068 , G06F13/1673 , G06F13/4068 , G11C29/52 , H03M13/03 , H03M13/29 , H03M13/35 , H03M13/6561 , Y02D10/14 , Y02D10/151
摘要： A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.
摘要翻译：半导体存储器件包括多个检测码发生器，其被配置为分别产生多个检测码以分别检测多个数据项中的错误;多个第一校正码发生器，被配置为产生多个第一校正码以校正错误在多个第一数据块中，分别包含数据项之一和相应检测码的第一数据块，被配置为生成用于校正第二数据块中的错误的第二校正码的第二校正码发生器，包含第一数据块的第二数据块，以及被配置为非易失性地存储第二数据块，第一校正码和第二校正码的半导体存储器。

6. 发明申请

US20130254633A1 DECODER, DECODING METHOD AND COMMUNICATION APPARATUS 有权
标题翻译：解码器，解码方法和通信装置
公开(公告)号：US20130254633A1
公开(公告)日：2013-09-26
申请号：US13746925
申请日：2013-01-22
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Haruka OBATA , Hironori UCHIKAWA
IPC分类号： H03M13/13
CPC分类号： H03M13/13 , H03M13/1111 , H03M13/3715 , H03M13/3746 , H03M13/3972
摘要： According to one embodiment, a decoder includes a control unit and a decoding unit. The control unit determines a window size applied to a first target frame to be a first value and determines a window size applied to a second target frame different from the first target frame to be a second value different from the first value. The decoding unit carries out windowed decoding of a spatially coupled code on the first target frame with the window size set to the first value and carries out windowed decoding of a spatially coupled code on the second target frame with the window size set to the second value.
摘要翻译：根据一个实施例，解码器包括控制单元和解码单元。控制单元将施加到第一目标帧的窗口大小确定为第一值，并且将应用于与第一目标帧不同的第二目标帧的窗口大小确定为不同于第一值的第二值。解码单元对第一目标帧上的空间耦合码进行窗口化解码，其窗口大小被设置为第一值，并且对第二目标帧执行窗口大小设置为第二值的空间耦合码的窗口化解码。

7. 发明申请

US20170220415A1 GLOBAL ERROR RECOVERY SYSTEM 有权
公开(公告)号：US20170220415A1
公开(公告)日：2017-08-03
申请号：US15011452
申请日：2016-01-29
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Daisuke HASHIMOTO , Hironori UCHIKAWA
IPC分类号： G06F11/10 , H03M13/11 , G06F3/06 , G11C29/52
CPC分类号： G06F11/1068 , G06F3/0619 , G06F3/064 , G06F3/0688 , G06F11/1048 , G11C29/52 , G11C2029/0411 , H03M13/1102 , H03M13/13 , H03M13/152 , H03M13/19 , H03M13/2909 , H03M13/293
摘要： In a network storage device that includes a plurality of data storage drives, error correction and/or recovery of data stored on one of the plurality of data storage drives is performed cooperatively by the drive itself and by a storage host that is configured to manage storage in the plurality of data storage drives. When an error-correcting code (ECC) operation performed by the drive cannot correct corrupted data stored on the drive, the storage host can attempt to correct the corrupted data based on parity and user data stored on the remaining data storage drives. In some embodiments, data correction can be performed iteratively between the drive and the storage host. Furthermore, the storage host can control latency associated with error correction by selecting a particular error correction process.

8. 发明申请

US20170075599A1 MEMORY SYSTEM, MEMORY CONTROLLER AND MEMORY CONTROL METHOD 有权
标题翻译：存储器系统，存储器控制器和存储器控制方法
公开(公告)号：US20170075599A1
公开(公告)日：2017-03-16
申请号：US15066298
申请日：2016-03-10
申请人： Kabushiki Kaisha Toshiba
发明人： Osamu TORII , Tokumasa HARA , Hironori UCHIKAWA
IPC分类号： G06F3/06 , G11C29/52 , G06F11/10
CPC分类号： G06F3/0619 , G06F3/0638 , G06F3/0679 , G06F11/1012 , G06F11/1068 , G11C29/52
摘要： According to an embodiment, a memory system includes: a non-volatile memory; an encoding unit that generates a code word in which zero and one occur at different occurrence rates by encoding data; and a control unit that writes k third data items and fourth data items into the non-volatile memory. The k is an integer larger than or equal to zero and smaller than or equal to n. The n is an integer larger than or equal to two. The k third data items are obtained by encoding k second data items with the encoding unit among first data items including n second data items and having a first data length. The fourth data items are obtained by removing data corresponding to the k third data items from the first data items. The third data items are generated by encoding the second data items with encoders, respectively.
摘要翻译：根据实施例，存储器系统包括：非易失性存储器; 编码单元，其通过编码数据生成其中以不同出现率出现零和一个的代码字; 以及将k个第三数据项和第四数据项写入非易失性存储器的控制单元。 k是大于或等于零且小于或等于n的整数。 n是大于或等于2的整数。通过在包括n个第二数据项的第一数据项中编码具有编码单元的k个第二数据项并具有第一数据长度来获得第k个数据项。通过从第一数据项中去除与第k个数据项对应的数据来获得第四数据项。第三数据项分别通过用编码器对第二数据项进行编码来产生。

9. 发明申请

US20150135035A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME 有权
公开(公告)号：US20150135035A1
公开(公告)日：2015-05-14
申请号：US14601664
申请日：2015-01-21
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Shinichi KANNO , Hironori UCHIKAWA
IPC分类号： G06F11/10 , H03M13/35
CPC分类号： H03M13/2906 , G06F11/10 , G06F11/1004 , G06F11/1008 , G06F11/1068 , G06F13/1673 , G06F13/4068 , G11C29/52 , H03M13/03 , H03M13/29 , H03M13/35 , H03M13/6561 , Y02D10/14 , Y02D10/151
摘要： A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.

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