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1. 发明授权

US11093581B2 Optimization problem solving calculation apparatus 有权
公开(公告)号：US11093581B2
公开(公告)日：2021-08-17
申请号：US16289084
申请日：2019-02-28
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Kosuke Tatsumura , Hayato Goto
IPC分类号： G06F17/16 , G06F17/13
摘要： A calculation apparatus according to an embodiment includes matrix multiplication circuitry, time evolution circuitry, management circuitry, and output circuitry. The matrix multiplication circuitry calculates N second intermediate variables at a first time point by matrix multiplication between N (N>=2) first intermediate variables at the first time point and a preset coefficient matrix in N rows and N columns. The time evolution circuitry calculates N first variables at a second time point and N first intermediate variables at the second time point, the second time point being a time point following one sampling period after the first time point. The management circuitry increments time point from a start time point for each sampling period and controls the above circuitry to perform a process for each time point. The output circuitry outputs N first variables at a preset end time point.

2. 发明授权

US10817304B2 Calculating device 有权
公开(公告)号：US10817304B2
公开(公告)日：2020-10-27
申请号：US16118646
申请日：2018-08-31
申请人： Kabushiki Kaisha Toshiba
发明人： Kosuke Tatsumura , Hayato Goto
IPC分类号： G06F9/38 , G06F7/72 , G06F9/30 , G06F7/57
摘要： According to one embodiment, a calculating device includes a first memory, a second memory, a third memory, a first arithmetic module, a second arithmetic module, a first conductive line electrically connecting a first output terminal of the first memory and a first input terminal of the first arithmetic module, a second conductive line electrically connecting a second output terminal of the first memory and a first input terminal of the second arithmetic module, a third conductive line electrically connecting a first output terminal of the second memory and a second input terminal of the second arithmetic module, a fourth conductive line electrically connecting a first output terminal of the third memory and a third input terminal of the second arithmetic module, and a fifth conductive line electrically connecting a first output terminal of the second arithmetic module and a second input terminal of the first arithmetic module.

3. 发明申请

US20180335973A1 COMPUTING DEVICE 审中-公开
公开(公告)号：US20180335973A1
公开(公告)日：2018-11-22
申请号：US15924690
申请日：2018-03-19
申请人： Kabushiki Kaisha Toshiba
发明人： Rie SATO , Koichi Mizushima , Hayato Goto
IPC分类号： G06F3/06
摘要： According to one embodiment, a computing device includes a first magnetic section, a first reading section, a memory section, and a computing section. The first reading section is configured to output a first signal corresponding to a magnetization state of a partial region of the first magnetic section. The computing section is configured to perform computation using the first signal when first information stored in the memory section is in a first state, and to perform computation using a reverse signal of the first signal when the first information is in a second state.

4. 发明授权

US10084436B2 Computing device comprising a josephson junction 有权
公开(公告)号：US10084436B2
公开(公告)日：2018-09-25
申请号：US15443277
申请日：2017-02-27
申请人： Kabushiki Kaisha Toshiba
发明人： Hayato Goto
IPC分类号： H03K3/38 , H01L39/02 , H01L39/22 , H03H11/04 , H03B15/00 , H01P5/02 , G06N99/00
CPC分类号： H03K3/38 , G06N10/00 , H01L39/025 , H01L39/223 , H01P5/02 , H03B15/003 , H03H11/04
摘要： According to one embodiment, a computing device includes a first conductive body, a first element, a second element, a first transmission line and a second transmission line. The first conductive body spreads along a first plane. The first element includes a Josephson junction and is separated from the first conductive body in a direction crossing the first plane. The second element includes a Josephson junction. The second element is separated from the first conductive body in the direction crossing the first plane. A direction from the first element toward the second element is along a first direction along the first plane. The first transmission line generates an electromagnetic field applied to the first element. The second transmission line generates an electromagnetic field applied to the second element.

5. 发明授权

US09130598B2 Decoding apparatus, decoding method, and decoding program for use in quantum error correction 有权
标题翻译：用于量子纠错的解码装置，解码方法和解码程序
公开(公告)号：US09130598B2
公开(公告)日：2015-09-08
申请号：US14065612
申请日：2013-10-29
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Hayato Goto , Hironori Uchikawa , Kouichi Ichimura , Satoshi Nakamura , Mamiko Kujiraoka
IPC分类号： H03M13/41 , H03M13/39 , H03M13/45
CPC分类号： H03M13/45 , G06N99/002 , H03M13/3905 , H03M13/3961 , H03M13/41 , H03M13/4107
摘要： According to one embodiment, a decoding apparatus includes first and second acquisition units, a holding unit, a calculation unit, and a decision unit. The first acquisition unit acquires first measurement values of measurements performed to measure an eigenvalue of an encoded Z operator to a first encoded qubit of the two encoded qubits. The second acquisition unit acquires second measurement values of measurements performed to measure an eigenvalue of an encoded X operator to a second encoded qubit of the two encoded qubits. The holding unit holds error probabilities for the first measurement values and the second measurement values. The calculation unit calculates probabilities for measurement values of an encoded Bell measurement by using the first measurement values, the second measurement values, and the error probabilities. The decision unit decides measurement values of the encoded Bell measurement, based on the calculated probabilities.
摘要翻译：根据一个实施例，解码装置包括第一和第二采集单元，保持单元，计算单元和判定单元。第一采集单元获取用于测量经编码的Z运算符的特征值到第二编码量子位的第一编码量子位的测量的第一测量值。第二采集单元获取用于测量编码X运算符的特征值到两个编码量子位的第二编码量子位的测量的第二测量值。保持单元保持第一测量值和第二测量值的误差概率。计算单元通过使用第一测量值，第二测量值和误差概率来计算编码贝尔测量的测量值的概率。决定单元基于所计算的概率来确定编码贝尔测量的测量值。

6. 发明授权

US11256779B2 Calculation apparatus, calculation method and computer program product 有权
公开(公告)号：US11256779B2
公开(公告)日：2022-02-22
申请号：US16801429
申请日：2020-02-26
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Taro Kanao , Kosuke Tatsumura , Hayato Goto
IPC分类号： G06F17/16
摘要： A calculation apparatus according to an embodiment includes one or more processing circuits configured to function as an interaction unit, a first addition unit, and a time evolution unit. The interaction unit generates N first intermediate variables obtained by performing a matrix computing on the N first variables and the coefficient matrix at the first time. The first addition unit calculates N second variables at the second time at which the sampling period elapses from the first time. The time evolution unit executes a time evolution process on the N second variables at the first time to generate N first variables at the second time. If the N first variables at the second time unsatisfied a predetermined constraint condition, the time evolution unit changes the N second variables at the second time in a direction of satisfying the constraint condition.

7. 发明授权

US11169732B2 Computing device 有权
公开(公告)号：US11169732B2
公开(公告)日：2021-11-09
申请号：US15924690
申请日：2018-03-19
申请人： Kabushiki Kaisha Toshiba
发明人： Rie Sato , Koichi Mizushima , Hayato Goto
IPC分类号： G06F3/06 , G11C5/02 , G11C11/16 , G11C11/54
摘要： According to one embodiment, a computing device includes a first magnetic section, a first reading section, a memory section, and a computing section. The first reading section is configured to output a first signal corresponding to a magnetization state of a partial region of the first magnetic section. The computing section is configured to perform computation using the first signal when first information stored in the memory section is in a first state, and to perform computation using a reverse signal of the first signal when the first information is in a second state.

8. 发明授权

US10860679B2 Calculating device, calculation program, recording medium, and calculation method 有权
公开(公告)号：US10860679B2
公开(公告)日：2020-12-08
申请号：US16123146
申请日：2018-09-06
申请人： Kabushiki Kaisha Toshiba
发明人： Hayato Goto , Kosuke Tatsumura
IPC分类号： G06F17/11 , G06F9/30
摘要： According to one embodiment, a calculating device includes a processor repeating a processing procedure. The processing procedure includes a first variable update and a second variable update. The first variable update includes updating an ith entry of a first variable xi by adding a first function to the ith entry of the first variable xi before the first variable update. The second variable update includes updating the ith entry of the second variable yi by adding a second function and a third function to the ith entry of the second variable yi before the second variable update. The processor performs at least an output of at least one of the ith entry of the first variable xi obtained after the repeating of the processing procedure or a function of the ith entry of the first variable xi obtained after the repeating of the processing procedure.

9. 发明授权

US10734569B2 Electronic circuit and calculating device 有权
公开(公告)号：US10734569B2
公开(公告)日：2020-08-04
申请号：US16276650
申请日：2019-02-15
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Hayato Goto
IPC分类号： H01L27/18 , H01L39/02 , H01L39/22 , G06N10/00
摘要： According to one embodiment, an electronic circuit includes a superconducting element and a supplier. The superconducting element includes first and second conductive components. The first conductive component includes first and second ends, and a first portion. The first end is capacitively coupled to a first quantum bit having a first characteristic frequency. The second end is capacitively coupled to a second quantum bit having a second characteristic frequency. The first portion is between the first and second ends. The second conductive component includes third end and fourth ends, and a Josephson junction provided between the third and fourth ends. The fourth end is capacitively coupled to the first portion. The supplier supplies a microwave to the third end. The microwave includes one of a first, a second, or a third wave. The second wave includes fourth and fifth waves. The third wave includes sixth and seventh waves.

10. 发明申请

US20190278610A1 CALCULATING DEVICE 审中-公开
公开(公告)号：US20190278610A1
公开(公告)日：2019-09-12
申请号：US16118646
申请日：2018-08-31
申请人： Kabushiki Kaisha Toshiba
发明人： Kosuke TATSUMURA , Hayato Goto
IPC分类号： G06F9/38 , G06F9/30 , G06F7/72
摘要： According to one embodiment, a calculating device includes a first memory, a second memory, a third memory, a first arithmetic module, a second arithmetic module, a first conductive line electrically connecting a first output terminal of the first memory and a first input terminal of the first arithmetic module, a second conductive line electrically connecting a second output terminal of the first memory and a first input terminal of the second arithmetic module, a third conductive line electrically connecting a first output terminal of the second memory and a second input terminal of the second arithmetic module, a fourth conductive line electrically connecting a first output terminal of the third memory and a third input terminal of the second arithmetic module, and a fifth conductive line electrically connecting a first output terminal of the second arithmetic module and a second input terminal of the first arithmetic module.

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