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1. 发明授权

US10325805B2 Method for manufacturing a semiconductor device 有权
公开(公告)号：US10325805B2
公开(公告)日：2019-06-18
申请号：US15651476
申请日：2017-07-17
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Masayuki Kitamura , Atsuko Sakata , Makoto Wada , Yuichi Yamazaki , Masayuki Katagiri , Akihiro Kajita , Tadashi Sakai , Naoshi Sakuma , Ichiro Mizushima
IPC分类号： H01L21/02 , H01L21/768 , H01L23/532
摘要： According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes forming a co-catalyst layer and catalyst layer above a surface of a semiconductor substrate. The co-catalyst layer and catalyst layer have fcc structure. The fcc structure is formed such that (111) face of the fcc structure is to be oriented parallel to the surface of the semiconductor substrate. The catalyst includes a portion which contacts the co-catalyst layer. The portion has the fcc structure. An exposed surface of the catalyst layer is planarized by oxidation and reduction treatments. A graphene layer is formed on the catalyst layer.

2. 发明授权

US09646933B2 Semiconductor device and manufacturing method thereof 有权
公开(公告)号：US09646933B2
公开(公告)日：2017-05-09
申请号：US15067116
申请日：2016-03-10
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Tatsuro Saito , Atsunobu Isobayashi , Akihiro Kajita , Tadashi Sakai
IPC分类号： H01L21/00 , H01L23/532 , H01L23/522 , H01L21/768
CPC分类号： H01L23/53276 , H01L21/76877 , H01L21/76886 , H01L23/5226 , H01L23/53295
摘要： According to one embodiment, a semiconductor device includes a first insulating layer on an underlying layer, a first trench formed in the first insulating layer, and a first graphene layer provided in the first trench. The first trench comprises a bottom surface on the underlying and two side surfaces joined to the bottom surface, formed into a U-shape. The first graphene layer has a stacked structure including a plurality of graphene sheets. The plurality of graphene sheets each include a depression in a central portion. Portions of the graphene sheets located in an edge of the first graphene layer are each extended upward, which is in a direction opposite to the bottom surface.

3. 发明授权

US09576905B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09576905B2
公开(公告)日：2017-02-21
申请号：US15052377
申请日：2016-02-24
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Taishi Ishikura , Atsunobu Isobayashi , Akihiro Kajita
IPC分类号： H01L21/768 , H01L23/528 , H01L23/532 , H01L27/115 , H01L21/311 , H01L21/8234 , H01L21/02
CPC分类号： H01L23/5283 , H01L21/02271 , H01L21/31116 , H01L21/76816 , H01L21/76877 , H01L21/76885 , H01L21/76895 , H01L21/823475 , H01L23/528 , H01L23/53214 , H01L23/53219 , H01L23/53228 , H01L23/53233 , H01L23/53242 , H01L23/53257 , H01L23/53276 , H01L23/5329 , H01L27/115
摘要： A semiconductor device includes a first wiring comprising a first conductive material on a semiconductor layer, a second wiring comprising the first conductive material on the semiconductor layer, a third wiring comprising a second conductive material different from the first conductive material, and an insulation film on the semiconductor layer between the first wiring and the second wiring and between the second wiring and the third wiring. The second wiring is provided on at least two sides of the third wiring, and a mean free path of free electrons in the first conductive material is shorter than a mean free path of free electrons in the second conductive material, or the first conductive material shows quantized conduction and the second conductive material does not show quantized conduction. The first wiring, the second wiring, the third wiring, and the insulation film are in one wiring layer provided on the semiconductor layer.
摘要翻译：一种半导体器件包括：第一布线，包括半导体层上的第一导电材料;第二布线，包括半导体层上的第一导电材料;第三布线，包括不同于第一导电材料的第二导电材料;以及绝缘膜，第一布线和第二布线之间以及第二布线和第三布线之间的半导体层。第二布线设置在第三布线的至少两侧，第一导电材料中的自由电子的平均自由程短于第二导电材料中的自由电子的平均自由程，或第一导电材料显示量化导电，第二导电材料不显示量子化导电。第一布线，第二布线，第三布线和绝缘膜位于设置在半导体层上的一个布线层中。

4. 发明授权

US09404880B1 Sensor and method of manufacturing sensor 有权
标题翻译：传感器和制造传感器的方法
公开(公告)号：US09404880B1
公开(公告)日：2016-08-02
申请号：US14848267
申请日：2015-09-08
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Tatsuro Saito , Masayuki Kitamura , Atsuko Sakata , Akihiro Kajita , Atsunobu Isobayashi , Tadashi Sakai
IPC分类号： H01L29/16 , G01N27/12
CPC分类号： G01N27/125 , H01L29/1606
摘要： The sensor includes a first graphene film that is provided on the insulating layer so as to be located in a flow path of a liquid containing the detection target substance, the first graphene film having a first edge that is parallel with a first direction that is along the flow path and a first edge that is parallel with a second direction that is different from the first direction, and the first graphene film having the shape of a band that extends in the second direction. The sensor includes a first electrode that is electrically connected to the first edge of the first graphene film that is parallel with the first direction. The sensor includes a second electrode that is electrically connected to a second edge of the first graphene film that is opposed to the first edge that is parallel with the first direction.
摘要翻译：传感器包括第一石墨烯膜，其设置在绝缘层上以便位于含有检测对象物质的液体的流路中，第一石墨烯膜具有与沿着第一方向平行的第一边缘所述流路和与所述第一方向不同的第二方向平行的第一边缘，所述第一石墨烯膜具有在所述第二方向上延伸的带状。传感器包括电连接到第一石墨烯膜的与第一方向平行的第一边缘的第一电极。传感器包括电连接到与第一方向平行的第一边缘相对的第一石墨烯膜的第二边缘的第二电极。

5. 发明授权

US08981569B2 Semiconductor device with low resistance wiring and manufacturing method for the device 有权
标题翻译：具有低电阻布线的半导体器件及器件的制造方法
公开(公告)号：US08981569B2
公开(公告)日：2015-03-17
申请号：US13842787
申请日：2013-03-15
申请人： Kabushiki Kaisha Toshiba
发明人： Tatsuro Saito , Makoto Wada , Atsunobu Isobayashi , Yuichi Yamazaki , Akihiro Kajita
IPC分类号： H01L23/48 , H01L23/522 , H01L21/768 , H01L21/02 , H01L23/532 , H01L51/00 , H01L51/44 , B82Y30/00
CPC分类号： H01L23/5226 , B82Y30/00 , H01L21/02606 , H01L21/76834 , H01L21/76838 , H01L21/76841 , H01L21/76843 , H01L21/76868 , H01L21/76876 , H01L21/76877 , H01L21/76879 , H01L21/76883 , H01L23/53276 , H01L51/0045 , H01L51/0048 , H01L51/444 , H01L2221/1094 , H01L2924/0002 , H01L2924/00
摘要： According to one embodiment, a semiconductor device includes an insulating film, a catalytic layer and a wiring layer. The insulating film has a hole. The catalytic layer is formed at the bottom of the hole, at the peripheral wall of the hole, and on the upper surface of the insulating film outside the hole. A contact is formed of a carbon nanotube provided on the portion of the catalytic layer at the bottom of the hole. The wiring layer is formed of graphene and provided on the catalytic layer outside the hole in contact with the carbon nanotube. The catalytic layer at the bottom of the hole is a perforated film, and the catalytic layer outside the hole is a continuous film.
摘要翻译：根据一个实施例，半导体器件包括绝缘膜，催化层和布线层。绝缘膜具有孔。催化层形成在孔的底部，孔的周壁处，并且在孔的外部的绝缘膜的上表面上形成。接触由设置在孔底部的催化剂层部分上的碳纳米管形成。布线层由石墨烯形成并设置在与碳纳米管接触的孔外的催化层上。孔底部的催化层是穿孔膜，孔外的催化层是连续膜。

6. 发明申请

US20140284802A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20140284802A1
公开(公告)日：2014-09-25
申请号：US14022505
申请日：2013-09-10
申请人： Kabushiki Kaisha Toshiba
发明人： Atsuko SAKATA , Masayuki Kitamura , Makoto Wada , Masayuki Katagiri , Yuichi Yamazaki , Akihiro Kajita
IPC分类号： H01L23/532 , H01L21/768
CPC分类号： H01L23/53276 , H01L21/76805 , H01L21/76849 , H01L21/7685 , H01L21/76852 , H01L23/5283 , H01L23/53238 , H01L23/53257 , H01L2924/0002 , H01L2924/00
摘要： According to one embodiment, a semiconductor device includes a metal interconnect and a graphene interconnect which are stacked to one another.
摘要翻译：根据一个实施例，半导体器件包括彼此堆叠的金属互连和石墨烯互连。

7. 发明授权

US09437716B2 Semiconductor device comprising a graphene wire 有权
公开(公告)号：US09437716B2
公开(公告)日：2016-09-06
申请号：US14803751
申请日：2015-07-20
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Makoto Wada , Yuichi Yamazaki , Akihiro Kajita , Atsunobu Isobayashi , Tatsuro Saito
IPC分类号： H01L29/66 , B82Y30/00 , H01L23/528 , H01L23/532 , C01B31/04
CPC分类号： H01L29/66977 , B82Y30/00 , C01B32/186 , H01L23/528 , H01L23/5283 , H01L23/53276 , H01L2924/0002 , Y10S977/734 , Y10S977/932 , H01L2924/00
摘要： According to one embodiment, a semiconductor device includes a catalyst underlying layer formed on a substrate including semiconductor elements formed thereon and processed in a wiring pattern, a catalyst metal layer that is formed on the catalyst underlying layer and whose width is narrower than that of the catalyst underlying layer, and a graphene layer growing with a sidewall of the catalyst metal layer set as a growth origin and formed to surround the catalyst metal layer.

8. 发明授权

US09236268B2 Manufacturing method of semiconductor device and lithography template 有权
标题翻译：半导体器件和光刻模板的制造方法
公开(公告)号：US09236268B2
公开(公告)日：2016-01-12
申请号：US14172641
申请日：2014-02-04
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Taishi Ishikura , Atsunobu Isobayashi , Akihiro Kajita
IPC分类号： H01L21/00 , H01L21/308 , H01L21/027 , H01L21/3105 , G03F7/00
CPC分类号： H01L21/3086 , G03F7/0002 , H01L21/0274 , H01L21/3105
摘要： In the manufacturing method of a semiconductor device according to the present embodiment, a resist is supplied on a base material. A template including a first template region having a device pattern and a second template region being adjacent to the device pattern and having supporting column patterns is pressed against the resist on the base material. The resist is cured, thereby transferring the device pattern to the resist on a first material region of the base material corresponding to the first template region and at the same time transferring the supporting column patterns to the resist on a second material region of the base material corresponding to the second template region to form supporting columns. The supporting columns are contacted with the first template region when the device pattern is transferred to a resist supplied to the second material region.
摘要翻译：在本实施方式的半导体装置的制造方法中，在基材上供给抗蚀剂。包括具有装置图案的第一模板区域和与装置图案相邻并且具有支撑柱图案的第二模板区域的模板被压靠在基材上的抗蚀剂上。抗蚀剂被固化，从而在对应于第一模板区域的基材的第一材料区域上将装置图案转印到抗蚀剂上，同时在基材的第二材料区域上将支撑柱图案转印到抗蚀剂上对应于第二模板区域以形成支撑柱。当将装置图案转移到提供给第二材料区域的抗蚀剂时，支撑柱与第一模板区域接触。

9. 发明申请

US20150262940A1 Semiconductor Device and Method of Manufacturing the Same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20150262940A1
公开(公告)日：2015-09-17
申请号：US14336134
申请日：2014-07-21
申请人： Kabushiki Kaisha Toshiba
发明人： Masayuki KITAMURA , Atsuko Sakata , Hisao MIYAZAKI , Akihiro Kajita , Tadashi Sakai
IPC分类号： H01L23/532 , H01L21/768 , H01L23/528 , H01L23/522
CPC分类号： H01L23/53276 , H01L21/76805 , H01L21/76814 , H01L21/76879 , H01L21/76897 , H01L23/522 , H01L23/5226 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L29/1606 , H01L2221/1094 , H01L2924/0002 , H01L2924/00
摘要： According to one embodiment, a semiconductor device includes a graphene interconnect, an insulation film formed on the graphene interconnect, and a via conducting portion formed in a via hole provided in the graphene interconnect and the insulation film.
摘要翻译：根据一个实施例，半导体器件包括石墨烯互连，形成在石墨烯互连上的绝缘膜和形成在设置在石墨烯互连中的通孔中的通孔导电部分和绝缘膜。

10. 发明授权

US09030012B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09030012B2
公开(公告)日：2015-05-12
申请号：US14155006
申请日：2014-01-14
申请人： Kabushiki Kaisha Toshiba
发明人： Makoto Wada , Akihiro Kajita , Atsunobu Isobayashi , Tatsuro Saito , Tadashi Sakai , Taishi Ishikura
IPC分类号： H01L23/52 , H01L23/544 , H01L23/532 , H01L21/768
CPC分类号： H01L23/544 , H01L21/76841 , H01L21/76877 , H01L23/5226 , H01L23/53276 , H01L2221/1094 , H01L2223/54426 , H01L2223/5446 , H01L2924/0002 , H01L2924/00
摘要： According to one embodiment, a semiconductor device includes a semiconductor substrate provided with a lower interconnect layer formed thereon, and having a device region and a mark formation region, a CNT via structure formed in the device region such that it contacts the lower interconnect layer, a first mark formed in the mark formation region, formed by embedding carbon nanotubes, and formed in the same layer as the CNT via structure, a second mark formed in the mark formation region of the semiconductor substrate, formed with no carbon nanotubes, and formed in the same layer as the CNT via structure and the first mark, and an interconnect layer formed on the CNT via structure and the first and second marks, and electrically connected to the CNT via structure.
摘要翻译：根据一个实施例，半导体器件包括设置有形成在其上的下部互连层并具有器件区域和标记形成区域的半导体衬底，在器件区域中形成的CNT通孔结构，使得其接触下部互连层，形成在标记形成区域中的第一标记，其通过包埋碳纳米管形成，并且形成在与CNT通孔结构相同的层中，形成在形成有无碳纳米管的半导体衬底的标记形成区域中的第二标记，并形成在CNT通孔结构和第一标记相同的层中，以及形成在CNT通孔结构和第一和第二标记上的互连层，并且电连接到CNT通孔结构。

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