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1. 发明申请

US20090098701A1 Method of manufacturing an integrated circuit 审中-公开
标题翻译：集成电路的制造方法
公开(公告)号：US20090098701A1
公开(公告)日：2009-04-16
申请号：US11974570
申请日：2007-10-15
申请人： Jurgen Faul , Martin Popp , Andrew Graham , Dongping Wu , Victor Verdugo
发明人： Jurgen Faul , Martin Popp , Andrew Graham , Dongping Wu , Victor Verdugo
IPC分类号： H01L21/336
CPC分类号： H01L21/26506 , H01L27/10876 , H01L29/4236 , H01L29/66621
摘要： The present invention provides a method of manufacturing an integrated circuit comprising the steps of: providing a semiconductor substrate, etching at least one trench into a surface of said semiconductor substrate, performing an ion implantation step, wherein a direction of said ion implantation step is parallel to a vertical centre line of said trench, and performing a single oxidation step to form a first oxide layer with a first layer thickness covering a bottom of said at least one trench and a second oxide layer with a second layer thickness covering the sidewalls of said at least one trench, wherein said first layer thickness differs from said second layer thickness.
摘要翻译：本发明提供一种制造集成电路的方法，包括以下步骤：提供半导体衬底，将至少一个沟槽蚀刻到所述半导体衬底的表面中，执行离子注入步骤，其中所述离子注入步骤的方向是平行的到所述沟槽的垂直中心线，并且执行单个氧化步骤以形成覆盖所述至少一个沟槽的底部的第一层厚度的第一氧化物层和覆盖所述至少一个沟槽的侧壁的第二层厚度的第二氧化物层至少一个沟槽，其中所述第一层厚度与所述第二层厚度不同。

2. 发明申请

US20090121286A1 Integrated Circuit Comprising a Field Effect Transistor and Method of Fabricating the Same 审中-公开
标题翻译：包含场效应晶体管的集成电路及其制造方法
公开(公告)号：US20090121286A1
公开(公告)日：2009-05-14
申请号：US11940034
申请日：2007-11-14
申请人： Matthias Goldbach , Jurgen Faul
发明人： Matthias Goldbach , Jurgen Faul
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/26513 , H01L29/517 , H01L29/6659 , H01L29/66621 , H01L29/7833 , H01L29/7834
摘要： An integrated circuit includes a field effect transistor including: a gate electrode disposed adjacent to a surface of semiconductor substrate and a source/drain region disposed in the semiconductor substrate and adjacent to the surface. A net dopant concentration of a first section of the source/drain region decreases towards the gate electrode along a direction perpendicular to the surface.
摘要翻译：集成电路包括场效应晶体管，该场效应晶体管包括：邻近半导体衬底的表面设置的栅电极和设置在半导体衬底中并邻近表面的源/漏区。源极/漏极区域的第一部分的净掺杂剂浓度沿垂直于该表面的方向朝向栅电极减小。

3. 发明授权

US07118955B2 Method for the production of a semiconductor substrate comprising a plurality of gate stacks on a semiconductor substrate, and corresponding semiconductor structure 有权
标题翻译：用于制造半导体衬底的包括多个栅叠层的半导体衬底的方法以及相应的半导体结构
公开(公告)号：US07118955B2
公开(公告)日：2006-10-10
申请号：US11010941
申请日：2004-12-10
申请人： Jurgen Amon , Jurgen Faul , Thomas Ruder , Thomas Schuster
发明人： Jurgen Amon , Jurgen Faul , Thomas Ruder , Thomas Schuster
IPC分类号： H01L21/8244
CPC分类号： H01L21/76897 , H01L27/10829 , H01L27/10888
摘要： Method for the production of a semiconductor structure comprising a plurality of gate stacks on a semiconductor substrate which serve as control electrodes for a respective selection transistor of a corresponding memory cell comprising a storage capacitor. Gate stacks are provided next to one another on the substrate provided with a gate dielectric wherein the gate stacks have a lower first layer made of polysilicon, an overlying second layer made of metal silicide, and an upper layer made of silicon nitride. A sidewall oxide is formed on uncovered sidewalls of the first and second layers of the gate stacks, and at least partly the sidewall oxide is removed on those sidewalls of the gate stacks serving as a control electrode which are remote from the associated storage capacitor. Silicon nitride sidewall spacers are then formed on the gate stacks.
摘要翻译：一种用于制造半导体结构的方法，该半导体结构包括半导体衬底上的多个栅叠层，其用作包括存储电容器的相应存储单元的相应选择晶体管的控制电极。在具有栅极电介质的基板上彼此相邻地设置栅极堆叠，其中栅极堆叠具有由多晶硅制成的较低的第一层，由金属硅化物制成的覆盖的第二层和由氮化硅制成的上层。侧壁氧化物形成在栅极堆叠的第一和第二层的未覆盖的侧壁上，并且至少部分地在用作远离相关联的存储电容器的控制电极的栅极堆叠的侧壁上去除侧壁氧化物。然后在栅极堆叠上形成氮化硅侧壁间隔物。

4. 发明授权

US07679120B2 Method for the production of a semiconductor substrate comprising a plurality of gate stacks on a semiconductor substrate, and corresponding semiconductor structure 失效
标题翻译：用于制造半导体衬底的包括多个栅叠层的半导体衬底的方法以及相应的半导体结构
公开(公告)号：US07679120B2
公开(公告)日：2010-03-16
申请号：US11513447
申请日：2006-08-31
申请人： Jurgen Amon , Jurgen Faul , Thomas Ruder , Thomas Schuster
发明人： Jurgen Amon , Jurgen Faul , Thomas Ruder , Thomas Schuster
IPC分类号： H01L27/108
CPC分类号： H01L21/76897 , H01L27/10829 , H01L27/10888
摘要： A semiconductor structure having a plurality of gate stacks on a semiconductor substrate provided with a gate dielectric. The gate stacks have a lower first layer made of polysilicon, an overlying second layer made of a metal silicide, and an upper third layer made of an insulating material, and a sidewall oxide on the sidewalls of the first and second layers. The sidewall oxide is thinned or removed on one of the sidewalls, and the gate stacks have sidewall spacers made of the insulating material.
摘要翻译：一种在具有栅极电介质的半导体衬底上具有多个栅极叠层的半导体结构。栅堆叠具有由多晶硅制成的较低的第一层，由金属硅化物制成的覆盖的第二层，以及由绝缘材料制成的上部第三层，以及在第一和第二层的侧壁上的侧壁氧化物。侧壁氧化物在一个侧壁上变薄或去除，并且栅极堆叠具有由绝缘材料制成的侧壁间隔物。

5. 发明申请

US20050124124A1 Method for fabricating a semiconductor structure 有权
标题翻译：半导体结构的制造方法
公开(公告)号：US20050124124A1
公开(公告)日：2005-06-09
申请号：US10995677
申请日：2004-11-23
申请人： Jurgen Amon , Jurgen Faul , Johann Alsmeier , Matthias Goldbach , Albrecht Kieslich , Ralf Muller , Dirk Offenberg , Thomas Schuster
发明人： Jurgen Amon , Jurgen Faul , Johann Alsmeier , Matthias Goldbach , Albrecht Kieslich , Ralf Muller , Dirk Offenberg , Thomas Schuster
IPC分类号： H01L27/108 , H01L21/265 , H01L21/8242 , H01L21/336
CPC分类号： H01L21/26586 , H01L27/10861 , H01L27/10873 , H01L27/10888
摘要： A method fabricates a semiconductor structure having a plurality of memory cells that are provided in a semiconductor substrate of a first conductivity type and contains a plurality of planar selection transistors and a corresponding plurality of storage capacitors connected thereto. The selection transistors have respective first and second active regions of a second conductivity type. The first active regions are connected to the storage capacitors and the second active regions are connected to respective bit lines, and respective gate stacks, which are provided above the semiconductor substrate in a manner insulated by a gate dielectric. In this case, a single-sided halo doping is effected, and an excessive outdiffusion of the halo doping zones is prevented by introduction of a diffusion-inhibiting species.
摘要翻译：一种制造半导体结构的方法，该半导体结构具有设置在第一导电类型的半导体衬底中的多个存储单元，并且包含多个平面选择晶体管和与其连接的对应的多个存储电容器。选择晶体管具有第二导电类型的相应的第一和第二有源区。第一有源区连接到存储电容器，并且第二有源区连接到以栅极电介质绝缘的方式设置在半导体衬底之上的相应位线和相应的栅极堆叠。在这种情况下，实现单面晕圈掺杂，并且通过引入扩散抑制物质来防止晕圈掺杂区的过度扩散。

6. 发明申请

US20050148178A1 METHOD FOR FABRICATING A P-CHANNEL FIELD-EFFECT TRANSISTOR ON A SEMICONDUCTOR SUBSTRATE 失效
标题翻译：在半导体基板上制造P沟道场效应晶体管的方法
公开(公告)号：US20050148178A1
公开(公告)日：2005-07-07
申请号：US10372989
申请日：2003-02-24
申请人： Johann Alsmeier , Jurgen Faul
发明人： Johann Alsmeier , Jurgen Faul
IPC分类号： H01L21/8238 , H01L29/49 , H01L29/78 , H01L21/302 , H01L21/461
CPC分类号： H01L29/4916 , H01L21/823842 , H01L29/7838 , Y10S438/91 , Y10S438/918 , Y10S438/919
摘要： A p-channel field-effect transistor is formed on a semiconductor substrate. The transistor has an n-doped gate electrode, a buried channel, a p-doped source and a p-doped drain. The transistor is fabricated by a procedure in which, after an implantation for defining an n-type well, an oxidation is performed to form a gate-oxide layer and n-doped polysilicon is subsequently deposited. The latter is doped with boron or boron fluoride particles either in situ or by a dedicated implantation step. In a thermal process, the boron acceptors penetrate through the oxide layer into the substrate of the n-type well, where they form a p-doped zone, which serves for counter doping and sets the threshold voltage. This results in a steep profile that permits a shallow buried channel. The control of the number particles penetrating through the oxide layer is achieved by nitriding the oxide layer in an N2O atmosphere.
摘要翻译：在半导体衬底上形成p沟道场效应晶体管。晶体管具有n掺杂栅电极，掩埋沟道，p掺杂源和p掺杂漏极。晶体管的制造方法是，在用于限定n型阱的注入之后，执行氧化以形成栅氧化层，随后沉积n掺杂多晶硅。后者在原位或通过专用注入步骤掺杂硼或氟化硼颗粒。在热处理中，硼受体穿过氧化物层进入n型阱的衬底，其中它们形成p掺杂区，用于反掺杂并设置阈值电压。这导致一个陡峭的轮廓，允许一个浅埋的通道。穿过氧化物层的数量颗粒的控制通过在N 2 O 2气氛中氮化氧化物层来实现。

7. 发明申请

US20050130370A1 Method for the production of a semiconductor substrate comprising a plurality of gate stacks on a semiconductor substrate, and corresponding semiconductor structure 有权
标题翻译：用于制造半导体衬底的包括多个栅叠层的半导体衬底的方法以及相应的半导体结构
公开(公告)号：US20050130370A1
公开(公告)日：2005-06-16
申请号：US11010941
申请日：2004-12-10
申请人： Jurgen Amon , Jurgen Faul , Thomas Ruder , Thomas Schuster
发明人： Jurgen Amon , Jurgen Faul , Thomas Ruder , Thomas Schuster
IPC分类号： H01L21/60 , H01L21/8242 , H01L27/108 , H01L29/04 , H01L29/10 , H01L31/036 , H01L31/0376 , H01L31/20
CPC分类号： H01L21/76897 , H01L27/10829 , H01L27/10888
摘要： Method for the production of a semiconductor structure comprising a plurality of gate stacks on a semiconductor substrate which serve as control electrodes for a respective selection transistor of a corresponding memory cell comprising a storage capacitor. Gate stacks are provided next to one another on the substrate provided with a gate dielectric wherein the gate stacks have a lower first layer made of polysilicon, an overlying second layer made of metal silicide, and an upper layer made of silicon nitride. A sidewall oxide is formed on uncovered sidewalls of the first and second layers of the gate stacks, and at least partly the sidewall oxide is removed on those sidewalls of the gate stacks serving as a control electrode which are remote from the associated storage capacitor. Silicon nitride sidewall spacers are then formed on the gate stacks.
摘要翻译：一种用于制造半导体结构的方法，该半导体结构包括半导体衬底上的多个栅叠层，其用作包括存储电容器的相应存储单元的相应选择晶体管的控制电极。在具有栅极电介质的基板上彼此相邻地设置栅极堆叠，其中栅极堆叠具有由多晶硅制成的较低的第一层，由金属硅化物制成的覆盖的第二层和由氮化硅制成的上层。侧壁氧化物形成在栅极堆叠的第一和第二层的未覆盖的侧壁上，并且至少部分地在用作远离相关联的存储电容器的控制电极的栅极堆叠的侧壁上去除侧壁氧化物。然后在栅极堆叠上形成氮化硅侧壁间隔物。

8. 发明申请

US20070205437A1 Method for the production of a semiconductor substrate comprising a plurality of gate stacks on a semiconductor substrate, and corresponding semiconductor structure 失效
标题翻译：用于制造半导体衬底的包括多个栅叠层的半导体衬底的方法以及相应的半导体结构
公开(公告)号：US20070205437A1
公开(公告)日：2007-09-06
申请号：US11513447
申请日：2006-08-31
申请人： Jurgen Amon , Jurgen Faul , Thomas Ruder , Thomas Schuster
发明人： Jurgen Amon , Jurgen Faul , Thomas Ruder , Thomas Schuster
IPC分类号： H01L29/76
CPC分类号： H01L21/76897 , H01L27/10829 , H01L27/10888
摘要： A semiconductor structure having a plurality of gate stacks on a semiconductor substrate provided with a gate dielectric. The gate stacks have a lower first layer made of polysilicon, an overlying second layer made of a metal silicide, and an upper third layer made of an insulating material, and a sidewall oxide on the sidewalls of the first and second layers. The sidewall oxide is thinned or removed on one of the sidewalls, and the gate stacks have sidewall spacers made of the insulating material.
摘要翻译：一种在具有栅极电介质的半导体衬底上具有多个栅极叠层的半导体结构。栅堆叠具有由多晶硅制成的较低的第一层，由金属硅化物制成的覆盖的第二层，以及由绝缘材料制成的上部第三层，以及在第一和第二层的侧壁上的侧壁氧化物。侧壁氧化物在一个侧壁上变薄或去除，并且栅极堆叠具有由绝缘材料制成的侧壁间隔物。

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