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1. 发明申请

US20110269280A1 SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110269280A1
公开(公告)日：2011-11-03
申请号：US13181583
申请日：2011-07-13
申请人： Junli Wang , Tomoyuki Hirano , Toyotaka Kataoka , Yoshiya Hagimoto
发明人： Junli Wang , Tomoyuki Hirano , Toyotaka Kataoka , Yoshiya Hagimoto
IPC分类号： H01L21/8234
CPC分类号： H01L21/82385 , H01L21/823425 , H01L21/823468 , H01L21/823475 , H01L21/823835 , H01L21/823857 , H01L21/823871 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device, including: a first group of transistors formed on a semiconductor substrate; and a second group of transistors formed on the semiconductor substrate, each of which is lower in operating voltage than each of the transistors in the first group; wherein each of the transistors in the first group includes a first gate electrode formed on the semiconductor substrate through a first gate insulating film, and a silicide layer formed on the first gate electrode; each of the transistors in the second group includes a second gate electrode formed in a trench for gate formation, formed in an insulating film above the semiconductor substrate, through a second gate insulating film; and a protective film is formed so as to cover the silicide layer on each of the first gate electrodes of the first group of transistors.
摘要翻译：一种半导体器件，包括：形成在半导体衬底上的第一组晶体管; 以及形成在所述半导体基板上的第二组晶体管，每个晶体管的工作电压低于所述第一组中的每个晶体管; 其中第一组中的每个晶体管包括通过第一栅极绝缘膜形成在半导体衬底上的第一栅电极和形成在第一栅电极上的硅化物层; 第二组中的每个晶体管包括形成在用于栅极形成的沟槽中的第二栅电极，其通过第二栅极绝缘膜形成在半导体衬底上方的绝缘膜中; 并且形成保护膜以覆盖第一晶体管组的每个第一栅电极上的硅化物层。

2. 发明授权

US07994603B2 Semiconductor device and a method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07994603B2
公开(公告)日：2011-08-09
申请号：US12168427
申请日：2008-07-07
申请人： Junli Wang , Tomoyuki Hirano , Toyotaka Kataoka , Yoshiya Hagimoto
发明人： Junli Wang , Tomoyuki Hirano , Toyotaka Kataoka , Yoshiya Hagimoto
IPC分类号： H01L21/70
CPC分类号： H01L21/82385 , H01L21/823425 , H01L21/823468 , H01L21/823475 , H01L21/823835 , H01L21/823857 , H01L21/823871 , H01L2924/0002 , H01L2924/00
摘要： Disclosed herein is a semiconductor device, including: a first group of transistors formed on a semiconductor substrate; and a second group of transistors formed on the semiconductor substrate, each of which is lower in operating voltage than each of the transistors in the first group; wherein each of the transistors in the first group includes a first gate electrode formed on the semiconductor substrate through a first gate insulating film, and a silicide layer formed on the first gate electrode; each of the transistors in the second group includes a second gate electrode formed in a trench for gate formation, formed in an insulating film above the semiconductor substrate, through a second gate insulating film; and a protective film is formed so as to cover the silicide layer on each of the first gate electrodes of the first group of transistors.
摘要翻译：本文公开了一种半导体器件，包括：形成在半导体衬底上的第一组晶体管; 以及形成在所述半导体基板上的第二组晶体管，每个晶体管的工作电压低于所述第一组中的每个晶体管; 其中第一组中的每个晶体管包括通过第一栅极绝缘膜形成在半导体衬底上的第一栅电极和形成在第一栅电极上的硅化物层; 第二组中的每个晶体管包括形成在用于栅极形成的沟槽中的第二栅电极，其通过第二栅极绝缘膜形成在半导体衬底上方的绝缘膜中; 并且形成保护膜以覆盖第一晶体管组的每个第一栅电极上的硅化物层。

3. 发明授权

US08367503B2 Semiconductor device and a method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08367503B2
公开(公告)日：2013-02-05
申请号：US13181583
申请日：2011-07-13
申请人： Junli Wang , Tomoyuki Hirano , Toyotaka Kataoka , Yoshiya Hagimoto
发明人： Junli Wang , Tomoyuki Hirano , Toyotaka Kataoka , Yoshiya Hagimoto
IPC分类号： H01L21/00
CPC分类号： H01L21/82385 , H01L21/823425 , H01L21/823468 , H01L21/823475 , H01L21/823835 , H01L21/823857 , H01L21/823871 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device, including: a first group of transistors formed on a semiconductor substrate; and a second group of transistors formed on the semiconductor substrate, each of which is lower in operating voltage than each of the transistors in the first group; wherein each of the transistors in the first group includes a first gate electrode formed on the semiconductor substrate through a first gate insulating film, and a silicide layer formed on the first gate electrode; each of the transistors in the second group includes a second gate electrode formed in a trench for gate formation, formed in an insulating film above the semiconductor substrate, through a second gate insulating film; and a protective film is formed so as to cover the silicide layer on each of the first gate electrodes of the first group of transistors.
摘要翻译：一种半导体器件，包括：形成在半导体衬底上的第一组晶体管; 以及形成在所述半导体基板上的第二组晶体管，每个晶体管的工作电压低于所述第一组中的每个晶体管; 其中第一组中的每个晶体管包括通过第一栅极绝缘膜形成在半导体衬底上的第一栅电极和形成在第一栅电极上的硅化物层; 第二组中的每个晶体管包括形成在用于栅极形成的沟槽中的第二栅电极，其通过第二栅极绝缘膜形成在半导体衬底上方的绝缘膜中; 并且形成保护膜以覆盖第一晶体管组的每个第一栅电极上的硅化物层。

4. 发明申请

US20090014812A1 SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090014812A1
公开(公告)日：2009-01-15
申请号：US12168427
申请日：2008-07-07
申请人： Junli Wang , Tomoyuki Hirano , Toyotaka Kataoka , Yoshiya Hagimoto
发明人： Junli Wang , Tomoyuki Hirano , Toyotaka Kataoka , Yoshiya Hagimoto
IPC分类号： H01L21/8236 , H01L27/088
CPC分类号： H01L21/82385 , H01L21/823425 , H01L21/823468 , H01L21/823475 , H01L21/823835 , H01L21/823857 , H01L21/823871 , H01L2924/0002 , H01L2924/00
摘要： Disclosed herein is a semiconductor device, including: a first group of transistors formed on a semiconductor substrate; and a second group of transistors formed on the semiconductor substrate, each of which is lower in operating voltage than each of the transistors in the first group; wherein each of the transistors in the first group includes a first gate electrode formed on the semiconductor substrate through a first gate insulating film, and a silicide layer formed on the first gate electrode; each of the transistors in the second group includes a second gate electrode formed in a trench for gate formation, formed in an insulating film above the semiconductor substrate, through a second gate insulating film; and a protective film is formed so as to cover the silicide layer on each of the first gate electrodes of the first group of transistors.
摘要翻译：本文公开了一种半导体器件，包括：形成在半导体衬底上的第一组晶体管; 以及形成在所述半导体基板上的第二组晶体管，每个晶体管的工作电压低于所述第一组中的每个晶体管; 其中第一组中的每个晶体管包括通过第一栅极绝缘膜形成在半导体衬底上的第一栅电极和形成在第一栅电极上的硅化物层; 第二组中的每个晶体管包括形成在用于栅极形成的沟槽中的第二栅电极，其通过第二栅极绝缘膜形成在半导体衬底上方的绝缘膜中; 并且形成保护膜以覆盖第一晶体管组的每个第一栅电极上的硅化物层。

5. 发明授权

US07538390B2 Semiconductor device with PMOS and NMOS transistors 有权
标题翻译：具有PMOS和NMOS晶体管的半导体器件
公开(公告)号：US07538390B2
公开(公告)日：2009-05-26
申请号：US11241108
申请日：2005-09-30
申请人： Junli Wang , Toyotaka Kataoka , Masaki Saito
发明人： Junli Wang , Toyotaka Kataoka , Masaki Saito
IPC分类号： H01L29/94 , H01L21/8238
CPC分类号： H01L27/1203 , H01L21/2007 , H01L21/823807 , H01L21/84 , H01L29/7842 , H01L29/78684
摘要： A semiconductor device including an NMOS region and a PMOS region in the same substrate, wherein the semiconductor device includes a strained Si layer which is provided on the substrate in the NMOS region and in which the surface has a plane orientation different from that of the substrate, and a strained SiGe layer which is provided on the substrate in the PMOS region and which is composed of a stained layer having the same plane orientation as that of the surface of the substrate; and a method of manufacturing the same.
摘要翻译：一种在同一衬底中包括NMOS区域和PMOS区域的半导体器件，其中半导体器件包括设置在NMOS区域中的衬底上并且其表面具有不同于衬底的平面取向的应变Si层以及设置在PMOS区域的基板上并由与基板表面相同的面取向的染色层构成的应变SiGe层; 及其制造方法。

6. 发明申请

US20060076622A1 Semiconductor device and method of manufacturing semiconductor device 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060076622A1
公开(公告)日：2006-04-13
申请号：US11241108
申请日：2005-09-30
申请人： Junli Wang , Toyotaka Kataoka , Masaki Saito
发明人： Junli Wang , Toyotaka Kataoka , Masaki Saito
IPC分类号： H01L27/12
CPC分类号： H01L27/1203 , H01L21/2007 , H01L21/823807 , H01L21/84 , H01L29/7842 , H01L29/78684
摘要： A semiconductor device including an NMOS region and a PMOS region in the same substrate, wherein the semiconductor device includes a strained Si layer which is provided on the substrate in the NMOS region and in which the surface has a plane orientation different from that of the substrate, and a strained SiGe layer which is provided on the substrate in the PMOS region and which is composed of a stained layer having the same plane orientation as that of the surface of the substrate; and a method of manufacturing the same.
摘要翻译：一种在同一衬底中包括NMOS区域和PMOS区域的半导体器件，其中半导体器件包括设置在NMOS区域中的衬底上并且其表面具有不同于衬底的平面取向的应变Si层以及设置在PMOS区域的基板上并由与基板表面相同的面取向的染色层构成的应变SiGe层; 及其制造方法。

7. 发明授权

US07871878B2 Method of fabricating PMOS and NMOS transistor on the same substrate 有权
标题翻译：在同一衬底上制造PMOS和NMOS晶体管的方法
公开(公告)号：US07871878B2
公开(公告)日：2011-01-18
申请号：US12425476
申请日：2009-04-17
申请人： Junli Wang , Toyotaka Kataoka , Masaki Saito
发明人： Junli Wang , Toyotaka Kataoka , Masaki Saito
IPC分类号： H01L21/8238 , H01L27/118
CPC分类号： H01L27/1203 , H01L21/2007 , H01L21/823807 , H01L21/84 , H01L29/7842 , H01L29/78684
摘要： A method of manufacturing a semiconductor device that includes a first and second device regions on a substrate. The method includes the steps of forming an insulation layer on the substrate, laminating a first semiconductor layer having a plane orientation different from the surface of the substrate on the insulation layer and exposing the substrate by removing the insulation layer and the first semiconductor layer from the second device region. A second semiconductor layer having the same plane orientation as the substrate and that is made of a strained layer is formed by epitaxial growth on the exposed substrate in the second device region.
摘要翻译：一种制造半导体器件的方法，其包括在衬底上的第一和第二器件区域。该方法包括以下步骤：在衬底上形成绝缘层，在绝缘层上层压具有不同于衬底表面的平面取向的第一半导体层，并通过从绝缘层上除去绝缘层和第一半导体层而暴露衬底第二设备区域。具有与衬底相同的平面取向并由应变层制成的第二半导体层通过在第二器件区域中暴露的衬底上外延生长而形成。

8. 发明申请

US20090221134A1 Semiconductor Device and Method of Manufacturing Semiconductor Device 有权
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：US20090221134A1
公开(公告)日：2009-09-03
申请号：US12425476
申请日：2009-04-17
申请人： Junli Wang , Toyotaka Kataoka , Masaki Saito
发明人： Junli Wang , Toyotaka Kataoka , Masaki Saito
IPC分类号： H01L21/20
CPC分类号： H01L27/1203 , H01L21/2007 , H01L21/823807 , H01L21/84 , H01L29/7842 , H01L29/78684
摘要： A method of manufacturing a semiconductor device that includes a first and second device regions on a substrate. The method includes the steps of forming an insulation layer on the substrate, laminating a first semiconductor layer having a plane orientation different from the surface of the substrate on the insulation layer and exposing the substrate by removing the insulation layer and the first semiconductor layer from the second device region. A second semiconductor layer having the same plane orientation as the substrate and that is made of a strained layer is formed by epitaxial growth on the exposed substrate in the second device region.
摘要翻译：一种制造半导体器件的方法，其包括在衬底上的第一和第二器件区域。该方法包括以下步骤：在衬底上形成绝缘层，在绝缘层上层压具有不同于衬底表面的平面取向的第一半导体层，并通过从绝缘层上除去绝缘层和第一半导体层而暴露衬底第二设备区域。具有与衬底相同的平面取向并由应变层制成的第二半导体层通过在第二器件区域中暴露的衬底上外延生长而形成。

9. 发明授权

US08857209B2 Apparatus for carrying/storing baked goods and the like 有权
标题翻译：用于携带/储存烘烤食品的装置等
公开(公告)号：US08857209B2
公开(公告)日：2014-10-14
申请号：US12932688
申请日：2011-03-03
申请人： Junli Wang
发明人： Junli Wang
IPC分类号： F25D3/08 , A47G19/26 , B65D85/36 , B65D81/38 , B65D45/22
CPC分类号： B65D81/382 , A47G19/26 , B65D45/22 , B65D85/36 , B65D2543/00361
摘要： An apparatus carries and stores foodstuffs in a desired ambient temperature, and comprises a primary tray, a shroud, and a lid. The primary tray comprises an inner support platform portion and an outer shroud-receiving portion. The shroud comprises an inner cover portion and an outer wall portion contiguous with the inner cover portion. The inner cover portion defines a downwardly open matter-receiving space for covering matter supported by the support platform portion. The outer wall portion and the inner cover portion define an upwardly open medium-receiving space for receiving and positioning a heat transfer medium adjacent the matter-receiving space. The lid is seatable upon the shroud for covering the medium-receiving space. A series of fastening mechanisms removably fasten the primary tray to the shroud. A heat transfer medium is receivable in the medium-receiving space for effecting heat transfer intermediate the medium-receiving and matter-receiving spaces.
摘要翻译：一种装置将食品携带并储存在期望的环境温度下，并且包括初级托盘，护罩和盖子。主托盘包括内支撑平台部分和外护罩接收部分。护罩包括内盖部分和与内盖部分邻接的外壁部分。内盖部分限定用于覆盖由支撑平台部分支撑的物体的向下开放的物质接纳空间。外壁部分和内盖部分限定向上开口的介质容纳空间，用于接收和定位邻近物体接收空间的传热介质。盖子可以安放在护罩上，用于覆盖介质容纳空间。一系列紧固机构将主托盘可拆卸地固定到护罩上。传热介质可以在介质接收空间中接收，用于在介质接收和物质接收空间之间进行热传递。

10. 发明申请

US20130113101A1 Use of Gas Cluster Ion Beam To Reduce Metal Void Formation In Interconnect Structures 有权
标题翻译：使用气体簇离子束减少互连结构中的金属空隙形成
公开(公告)号：US20130113101A1
公开(公告)日：2013-05-09
申请号：US13290577
申请日：2011-11-07
申请人： Kangguo Cheng , Junli Wang , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Kangguo Cheng , Junli Wang , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L23/52 , H01L21/768
CPC分类号： H01L21/76804 , H01L21/76814 , H01L21/76825 , H01L21/76865 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A gas cluster ion beam process is used to reduce and/or even eliminate metal void formation in an interconnect structure. In one embodiment, gas cluster ion beam etching forms a chamfer opening in an interconnect dielectric material. In another embodiment, gas cluster ion beam etching reduces the overhang profile of a diffusion barrier or a multilayered stack of a diffusion barrier and a plating seed layer that is formed within an opening located in an interconnect dielectric material. In yet another embodiment, a gas cluster ion beam process deactivates a surface of an interconnect dielectric material that is located at upper corners of an opening that is formed therein. In this embodiment, the gas cluster ion beam process deposits a material that deactivates the upper corners of each opening that is formed into an interconnect dielectric material.
摘要翻译：使用气体簇离子束工艺来减少和/或甚至消除互连结构中的金属空隙形成。在一个实施例中，气体簇离子束蚀刻在互连电介质材料中形成倒角开口。在另一个实施方案中，气体簇离子束蚀刻减少扩散阻挡层或扩散阻挡层的多层堆叠和形成在位于互连电介质材料中的开口内的电镀种子层的悬垂分布。在另一个实施例中，气体团簇离子束过程使位于其中形成的开口的上角的互连电介质材料的表面失活。在该实施例中，气体簇离子束处理沉积了使形成为互连电介质材料的每个开口的上角失活的材料。

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