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1. 发明授权

US08309253B2 Titanium oxide, method for manufacturing the same, and lithium secondary battery using the same as active material 有权
标题翻译：氧化钛，其制造方法以及使用该二氧化钛作为活性物质的锂二次电池
公开(公告)号：US08309253B2
公开(公告)日：2012-11-13
申请号：US12530035
申请日：2008-03-05
申请人： Junji Akimoto , Norihito Kijima , Hiroshi Hayakawa , Yasuhiko Takahashi , Yasushi Idemoto
发明人： Junji Akimoto , Norihito Kijima , Hiroshi Hayakawa , Yasuhiko Takahashi , Yasushi Idemoto
IPC分类号： H01M4/13
CPC分类号： H01M4/485 , C01G23/04 , C01P2002/72 , C01P2002/77 , C01P2004/03 , C01P2006/40 , H01M10/052
摘要： The present invention relates to a novel compound characterized by having a one-dimensional tunnel structure and being represented by the chemical formula H2Ti12O25, a method for manufacturing the same, and a lithium secondary battery containing, as a constituent thereof, an electrode produced by using the novel titanium oxide as an active material, and expected to demonstrate superior charge/discharge cycle characteristics over a long period of time as well as high capacity.
摘要翻译：本发明涉及一种具有一维隧道结构并由化学式H2Ti12O25表示的新型化合物及其制造方法，以及锂二次电池作为其组成成分，该电极通过使用新型氧化钛作为活性物质，并且预期在长时间和高容量下表现出优异的充电/放电循环特性。

2. 发明授权

US08193146B2 Method of ameliorating symptom caused by mood disturbance 失效
标题翻译：改善情绪障碍引起的症状的方法
公开(公告)号：US08193146B2
公开(公告)日：2012-06-05
申请号：US11908912
申请日：2006-03-15
申请人： Yasuhiko Takahashi , Kenji Oeda
发明人： Yasuhiko Takahashi , Kenji Oeda
IPC分类号： A61K38/00 , A61K48/00
CPC分类号： C12N15/8509 , A01K67/0275 , A01K2217/05 , A01K2227/105 , A01K2267/0356 , A61K38/00 , A61K48/005 , C07K14/47 , C12N2830/008 , G01N33/5088 , G01N33/6893 , G01N2800/304
摘要： The present invention relates to a method for improving symptom of mood disorder or its related disorder comprising a step of allowing Gm1 protein and the like to be excessively present in a brain of a mammal, and a non-human mammal, to which the method has been applied, and the like.
摘要翻译：本发明涉及一种改善情绪障碍或其相关疾病症状的方法，包括使Gm1蛋白等过量存在于哺乳动物和非人哺乳动物的脑中的步骤，该方法具有被应用等。

3. 发明授权

US07598133B2 Semiconductor memory device and a method of manufacturing the same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US07598133B2
公开(公告)日：2009-10-06
申请号：US11714865
申请日：2007-03-07
申请人： Masahiro Moniwa , Hiraku Chakihara , Kousuke Okuyama , Yasuhiko Takahashi
发明人： Masahiro Moniwa , Hiraku Chakihara , Kousuke Okuyama , Yasuhiko Takahashi
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/331 , H01L21/76
CPC分类号： H01L27/11 , G11C11/412 , H01L27/1104
摘要： A memory cell of an SRAM has two drive MISFETs and two vertical MISFETs. The p channel vertical MISFETs are formed above the n channel drive MISFETs. The vertical MISFETs respectively mainly comprise laminate formed of a lower semiconductor layer, intermediate semiconductor layer and upper semiconductor layer laminated in this sequence, a gate insulating film of silicon oxide formed on the surface of the side wall of the laminate, and a gate electrode formed so as to cover the side wall of the laminate. The vertical MISFETs are perfect depletion type MISFETs.
摘要翻译： SRAM的存储单元具有两个驱动MISFET和两个垂直MISFET。 p沟道垂直MISFET形成在n沟道驱动MISFET的上方。垂直MISFET分别主要包括由下半导体层，中间半导体层和按此顺序层叠的上半导体层形成的叠层，形成在层叠体的侧壁表面上的氧化硅栅绝缘膜和形成的栅电极以覆盖层压板的侧壁。垂直MISFET是完全耗尽型MISFET。

4. 发明授权

US07460392B2 Semiconductor memory device and semiconductor integrated circuit 失效
标题翻译：半导体存储器件和半导体集成电路
公开(公告)号：US07460392B2
公开(公告)日：2008-12-02
申请号：US11979128
申请日：2007-10-31
申请人： Yasuhiko Takahashi , Takayuki Tanaka
发明人： Yasuhiko Takahashi , Takayuki Tanaka
IPC分类号： G11C11/00
CPC分类号： H01L27/1203 , G11C11/412 , H01L27/1104 , Y10S257/903 , Y10S257/904
摘要： In a semiconductor memory device, third and fourth transistors are configured as a vertical structure. The third transistor is laminated over a first transistor, and the fourth transistor is laminated over a second transistor, whereby a reduction in cell area is achieved. A voltage, which is set on the condition that the difference between a source potential applied to each of the first and second transistors and the potential of a select level of a word line becomes greater than or equal to a threshold voltage of each of the third and fourth transistors, is supplied to a source electrode of each of the first and second transistors, to thereby perform “0” write compensation.
摘要翻译：在半导体存储器件中，第三和第四晶体管被构造为垂直结构。第三晶体管层叠在第一晶体管上，并且第四晶体管层叠在第二晶体管上，由此实现单元面积的减小。在施加到第一和第二晶体管中的每一个的源极电位之间的差与字线的选择电平的电位变得大于或等于第三个晶体管的每一个的阈值电压的条件下设置的电压和第四晶体管，被提供给第一和第二晶体管的每一个的源极，从而执行“0”写入补偿。

5. 发明申请

US20070173006A1 Semiconductor memory device and a method of manufacturing the same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20070173006A1
公开(公告)日：2007-07-26
申请号：US11714865
申请日：2007-03-07
申请人： Masahiro Moniwa , Hiraku Chakihara , Kousuke Okuyama , Yasuhiko Takahashi
发明人： Masahiro Moniwa , Hiraku Chakihara , Kousuke Okuyama , Yasuhiko Takahashi
IPC分类号： H01L21/8234
CPC分类号： H01L27/11 , G11C11/412 , H01L27/1104
摘要： A memory cell of an SRAM has two drive MISFETs and two vertical MISFETs. The p channel vertical MISFETs are formed above the n channel drive MISFETs. The vertical MISFETs respectively mainly comprise laminate formed of a lower semiconductor layer, intermediate semiconductor layer and upper semiconductor layer laminated in this sequence, a gate insulating film of silicon oxide formed on the surface of the side wall of the laminate, and a gate electrode formed so as to cover the side wall of the laminate. The vertical MISFETs are perfect depletion type MISFETs.
摘要翻译： SRAM的存储单元具有两个驱动MISFET和两个垂直MISFET。 p沟道垂直MISFET形成在n沟道驱动MISFET的上方。垂直MISFET分别主要包括由下半导体层，中间半导体层和按此顺序层叠的上半导体层形成的叠层，形成在层叠体的侧壁表面上的氧化硅栅绝缘膜和形成的栅电极以覆盖层压板的侧壁。垂直MISFET是完全耗尽型MISFET。

6. 发明授权

US07246284B2 Integration type input circuit and method of testing it 有权
标题翻译：集成型输入电路及其测试方法
公开(公告)号：US07246284B2
公开(公告)日：2007-07-17
申请号：US10928179
申请日：2004-08-30
申请人： Yasuhiko Takahashi
发明人： Yasuhiko Takahashi
IPC分类号： G01R31/28
CPC分类号： G01R31/31701
摘要： An input interface circuit is provided which includes an input transistor for receiving a digital input signal, a circuit for generating a reference value, and an integrating capacitor connected in series to a pair of current conducting electrodes of the input transistor for integrating the input signal. A logic level of the input signal is discriminated by comparing an integration of the input signal with the reference value. To provide a testing function, a test transistor is connected to a junction between the pair of current conducting electrodes of the input transistor and the integrating capacitor so that a current driving capability may be determined. Additionally, a discharge path circuit for controllably discharging the integrating capacitor is connected to the junction between the input transistor and the integrating capacitor.
摘要翻译：提供一种输入接口电路，其包括用于接收数字输入信号的输入晶体管，用于产生参考值的电路，以及串联连接到用于积分输入信号的输入晶体管的一对电流传导电极的积分电容器。通过比较输入信号与基准值的积分来区分输入信号的逻辑电平。为了提供测试功能，测试晶体管连接到输入晶体管的一对电流传导电极和积分电容器之间的结，使得可以确定电流驱动能力。此外，用于可控放电积分电容器的放电路径电路连接到输入晶体管和积分电容器之间的结。

7. 发明授权

US06606277B2 Semiconductor memory device 失效
公开(公告)号：US06606277B2
公开(公告)日：2003-08-12
申请号：US09925417
申请日：2001-08-10
申请人： Yasuhiko Takahashi
发明人： Yasuhiko Takahashi
IPC分类号： G11C800
CPC分类号： G11C7/22 , G11C8/12 , G11C11/409 , G11C2207/2281 , G11C2207/229
摘要： To provide a semiconductor memory device which has high speed operation and multifunctionality, and is suitable for 3D imaging. Data is output to a data terminal in synchronism with a synchronization signal during data read, write data is input via the data terminal in synchronism with a synchronization signal during data write, input of write data via the data terminal is permitted via the data terminal in a first period wherein output of read data to the data terminal should be performed, a second period is provided from when a write specification is issued to when input of write data starts, and a third period is provided during which input of write data is performed.

8. 发明授权

US06448832B1 Variable delay circuit 失效
标题翻译：可变延迟电路
公开(公告)号：US06448832B1
公开(公告)日：2002-09-10
申请号：US10036463
申请日：2002-01-07
申请人： Yasuhiko Takahashi
发明人： Yasuhiko Takahashi
IPC分类号： H03H1120
CPC分类号： H03L7/0805 , G06F1/10 , H03L7/0814 , H03L7/085
摘要： In an high-frequency LSI chip, a clock signal generating circuit which establish accurate synchronism between an input clock signal and an internal clock signal to prevent an input circuit to cause a synchronization shift. The clock signal generating circuit includes an input circuit for amplifying an input signal and outputting an amplified signal as a first internal signal; a variable delay circuit, on the basis of a control signal, for delaying the first internal signal and outputting a delayed signal as a second internal signal; a phase comparator for finding a phase difference between the input signal and second internal signal and outputting a phase difference signal indicative of the phase difference; and a control circuit for generating the control signal on the basis of the phase difference signal. Thereby the influences of a delay caused by the input circuit, which would not be able to be avoided in the prior art, can be avoided and thus the accurate internal clock signal can be generated.
摘要翻译：在高频LSI芯片中，时钟信号发生电路在输入时钟信号和内部时钟信号之间建立精确的同步，以防止输入电路引起同步偏移。时钟信号发生电路包括用于放大输入信号并输出放大信号作为第一内部信号的输入电路; 基于控制信号的可变延迟电路，用于延迟所述第一内部信号并输出延迟的信号作为第二内部信号; 相位比较器，用于求出输入信号和第二内部信号之间的相位差，并输出指示相位差的相位差信号; 以及控制电路，用于根据相位差信号产生控制信号。因此，可以避免在现有技术中不能避免的由输入电路引起的延迟的影响，从而可以产生精确的内部时钟信号。

9. 发明授权

US06265869B1 Method of detecting thermal asperity of magnetic storage device and circuit thereof 有权
标题翻译：检测磁存储器件的热不均匀性及其电路的方法
公开(公告)号：US06265869B1
公开(公告)日：2001-07-24
申请号：US09206472
申请日：1998-12-07
申请人： Yasuhiko Takahashi
发明人： Yasuhiko Takahashi
IPC分类号： G01R3312
CPC分类号： G11B20/24 , G11B5/012 , G11B5/035 , G11B5/09 , G11B19/04 , G11B2005/0016
摘要： Disclosed are a method of detecting a thermal asperity of a magnetic storage device which detects that a magnetic resistance element comes into contact with a magnetic storage medium, and a circuit thereof. This method comprises detecting an amplitude of an output of the magnetic resistance element, and creating a slice level that is m-times (m>1) as large as an output level. The slice level of an output relative value is created from the output of the magnetic resistance element, and hence the slice level having a magnitude corresponding to the output level of each magnetic resistance element can be automatically created. It is therefore feasible to accurately detect the thermal asperity of each magnetic resistance element.
摘要翻译：公开了一种检测磁性元件与磁性存储介质接触的磁存储装置的热凹凸的方法及其电路。该方法包括检测磁阻元件的输出的幅度，并产生与输出电平一样大的m倍（m> 1）的限幅电平。从磁阻元件的输出产生输出相对值的限制电平，因此可以自动产生具有对应于每个磁阻元件的输出电平的幅度的限幅电平。因此，精确地检测每个磁阻元件的热不均匀性是可行的。

10. 发明授权

US6070257A Integration type input circuit and method of testing it 失效
公开(公告)号：US6070257A
公开(公告)日：2000-05-30
申请号：US996184
申请日：1997-12-22
申请人： Yasuhiko Takahashi
发明人： Yasuhiko Takahashi
IPC分类号： G01R31/28 , G01R31/317 , G11C29/56
CPC分类号： G01R31/31701
摘要： An input interface circuit is provided. The circuit includes an input transistor for receiving a digital input signal, a circuit for generating a reference value, and an integrating capacitor connected in series to a pair of current conducting electrodes of the input transistor for integrating the input signal. A logic level of the input signal is discriminated by comparing an integration of the input signal with the reference value. To provide a testing function, a test transistor is connected to a junction between the pair of current conducting electrodes of the input transistor and the integrating capacitor so that a current driving capability may be determined. Additionally, a discharge path circuit for controllably discharging the integrating capacitor is connected to the junction between the input transistor and the integrating capacitor.

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