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1. 发明申请

US20110267893A1 NON-VOLATILE SEMICONDUCTOR MEMORY AND MEMORY SYSTEM 审中-公开
标题翻译：非易失性半导体存储器和存储器系统
公开(公告)号：US20110267893A1
公开(公告)日：2011-11-03
申请号：US13180148
申请日：2011-07-11
申请人： Junichi KATO , Hideto Kotani
发明人： Junichi KATO , Hideto Kotani
IPC分类号： G11C16/34
CPC分类号： G11C16/06 , G11C16/28 , G11C16/3454
摘要： A non-volatile semiconductor memory determines that a given memory cell in an array is at a predetermined threshold voltage in a determination circuit by comparing a current of the memory cell with a reference current in a sense amplifier circuit. A reference current generation circuit includes a current variable device adjusting the reference current. A current adjustment amount calculator receives address information of the memory cell of which threshold voltage is determined and calculates a current adjustment amount corresponding to the address information. The current variable device adjusts the reference current based on the calculated current adjustment amount. Therefore, even when characteristics of interconnects coupled to the sense amplifier circuit, the target memory cell, and the sense amplifier vary, an offset amount between an actual threshold and an apparent threshold is eliminated to reduce electric stress applied to the memory cell in a rewrite operation.
摘要翻译：非易失性半导体存储器通过将存储单元的电流与读出放大器电路中的参考电流进行比较来确定阵列中的给定存储单元在确定电路中处于预定的阈值电压。参考电流产生电路包括调整参考电流的电流可变器件。当前调整量计算器接收确定了阈值电压的存储单元的地址信息，并计算与地址信息对应的当前调整量。电流可变装置根据计算出的电流调整量来调整基准电流。因此，即使当耦合到读出放大器电路，目标存储器单元和读出放大器的互连的特性变化时，消除实际阈值和表观阈值之间的偏移量，以减少在重写中施加到存储器单元的电应力操作。

2. 发明授权

US07460410B2 Nonvolatile semiconductor memory device and programming or erasing method therefor 有权
标题翻译：非易失性半导体存储器件及其编程或擦除方法
公开(公告)号：US07460410B2
公开(公告)日：2008-12-02
申请号：US11502430
申请日：2006-08-11
申请人： Hiroyasu Nagai , Masahiro Toki , Kenji Misumi , Hideto Kotani
发明人： Hiroyasu Nagai , Masahiro Toki , Kenji Misumi , Hideto Kotani
IPC分类号： G11C16/00
CPC分类号： G11C16/349
摘要： In a nonvolatile memory cell having a trap layer, programming or erasing is made in a sequence of first charge injection with a given wait time being secured and second charge injection executed after the first charge injection. Surrounding charge that deteriorates the data retention characteristic is reduced by use of initial variation occurring immediately after programming (charge loss phenomenon due to binding of injected charge with the surrounding charge in an extremely short time), and then the charge loss due to the initial variation is compensated, to thereby improve the data retention characteristic.
摘要翻译：在具有陷阱层的非易失性存储单元中，按照第一次电荷注入的顺序进行编程或擦除，同时确保给定的等待时间，并且在第一次电荷注入之后执行第二次电荷注入。通过使用编程后立即发生的初始变化（由于注入的电荷与周围电荷的结合在极短的时间内导致的电荷损失现象），从而降低数据保持特性的周围电荷，然后由于初始变化引起的电荷损失被补偿，从而提高数据保持特性。

3. 发明申请

US20100022404A1 Gene/protein marker for prediction or diagnosis of pharmacological efficacy of aurora a inhibitor 审中-公开
标题翻译：用于预测或诊断极光抑制剂药理功效的基因/蛋白质标记
公开(公告)号：US20100022404A1
公开(公告)日：2010-01-28
申请号：US12311535
申请日：2007-10-05
申请人： Shinichi Hasako , Koji Ichikawa , Hideto Kotani , Satomi Miki , Katsuyoshi Miyama , Toshiyasu Shimomura , Kazuhiko Takahashi , Kazunori Yamanaka
发明人： Shinichi Hasako , Koji Ichikawa , Hideto Kotani , Satomi Miki , Katsuyoshi Miyama , Toshiyasu Shimomura , Kazuhiko Takahashi , Kazunori Yamanaka
IPC分类号： C40B30/04 , C07H21/04 , C40B40/08 , C07K14/00 , C40B40/10
CPC分类号： C12Q1/6883 , A61K49/0004 , C12Q2600/158 , G01N33/5082 , G01N2333/912
摘要： [PROBLEMS] To provide: a gene marker or a protein marker for detecting whether or not an Aurora A inhibitor acts in a living body in an Aurora A-specific manner when the Aurora A inhibitor is administered to the living body; and a method for predicting or diagnosing the pharmacological efficacy of an Aurora A inhibitor by using the gene marker or the protein marker [MEANS FOR SOLVING PROBLEMS] A gene/protein marker for use in the prediction or diagnosis of the pharmacological efficacy of an Aurora A inhibitor, wherein the gene is a gene selected from the group consisting of Aurora B, Histone H3, BIRC5, PRC1, DLG7, TACC3 and KNTC2 or a gene having substantially the same function as that of the gene; and a method for predicting or diagnosing the pharmacological efficacy of an Aurora A inhibitor by using the gene/protein marker.
摘要翻译： [问题]提供：当将Aurora A抑制剂施用于生物体时，用于检测Aurora A抑制剂是否以Aurora A特异性方式作用于活体中的基因标记物或蛋白质标记物; 以及通过使用基因标记或蛋白质标记来预测或诊断Aurora A抑制剂的方法[用于解决问题]用于预测或诊断Aurora A的药理学功效的基因/蛋白质标记抑制剂，其中所述基因是选自Aurora B，组蛋白H3，BIRC5，PRC1，DLG7，TACC3和KNTC2的基因或与基因具有基本相同功能的基因; 以及通过使用基因/蛋白质标记物来预测或诊断Aurora A抑制剂的药理功效的方法。

4. 发明申请

US20070165460A1 Nonvolatile semiconductor memory device and programming or erasing method therefor 审中-公开
标题翻译：非易失性半导体存储器件及其编程或擦除方法
公开(公告)号：US20070165460A1
公开(公告)日：2007-07-19
申请号：US11633586
申请日：2006-12-05
申请人： Masahiro Toki , Hiroyasu Nagai , Kenji Misumi , Hideto Kotani
发明人： Masahiro Toki , Hiroyasu Nagai , Kenji Misumi , Hideto Kotani
IPC分类号： G11C16/04 , G11C16/06 , G11C11/34
CPC分类号： G11C16/0466 , G11C11/5671 , G11C16/10 , G11C16/16
摘要： In a nonvolatile memory cell having a trap layer, by executing first charge injection with a given wait time being secured and second charge injection after the first charge injection in a programming or erasing sequence, surrounding charge that may deteriorate the data retention characteristic is reduced utilizing an initial variation (charge loss phenomenon caused by binding of injected charge with the surrounding charge in an extremely short time) occurring immediately after programming. Thereafter, the charge loss in the initial variation is compensated, so that the subsequent data retention characteristic is improved. The second charge injection is executed only when a predetermined determination level has been reached.
摘要翻译：在具有陷阱层的非易失性存储单元中，通过在编程或擦除顺序中以给定的等待时间执行第一次充电注入和第一次充电注入之后的第二次充电注入，利用可能劣化数据保持特性的周围电荷来利用在编程之后立即出现初始变化（由注入的电荷与极短时间内的周围电荷的结合引起的电荷损失现象）。此后，补偿初始变化中的电荷损失，从而提高随后的数据保持特性。仅在已经达到预定的确定水平时执行第二次充电注入。

5. 发明申请

US20070047318A1 Nonvolatile semiconductor memory device and programming or erasing method therefor 有权
标题翻译：非易失性半导体存储器件及其编程或擦除方法
公开(公告)号：US20070047318A1
公开(公告)日：2007-03-01
申请号：US11502430
申请日：2006-08-11
申请人： Hiroyasu Nagai , Masahiro Toki , Kenji Misumi , Hideto Kotani
发明人： Hiroyasu Nagai , Masahiro Toki , Kenji Misumi , Hideto Kotani
IPC分类号： G11C16/04
CPC分类号： G11C16/349
摘要： In a nonvolatile memory cell having a trap layer, programming or erasing is made in a sequence of first charge injection with a given wait time being secured and second charge injection executed after the first charge injection. Surrounding charge that deteriorates the data retention characteristic is reduced by use of initial variation occurring immediately after programming (charge loss phenomenon due to binding of injected charge with the surrounding charge in an extremely short time), and then the charge loss due to the initial variation is compensated, to thereby improve the data retention characteristic.
摘要翻译：在具有陷阱层的非易失性存储单元中，按照第一次电荷注入的顺序进行编程或擦除，同时确保给定的等待时间，并且在第一次电荷注入之后执行第二次电荷注入。通过使用编程后立即发生的初始变化（由于注入的电荷与周围电荷的结合在极短的时间内导致的电荷损失现象），从而降低数据保持特性的周围电荷，然后由于初始变化引起的电荷损失被补偿，从而提高数据保持特性。

6. 发明申请

US20060181929A1 Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：US20060181929A1
公开(公告)日：2006-08-17
申请号：US11354066
申请日：2006-02-15
申请人： Hideto Kotani , Satoshi Mishima , Masahiro Toki , Hoshihide Haruyama
发明人： Hideto Kotani , Satoshi Mishima , Masahiro Toki , Hoshihide Haruyama
IPC分类号： G11C11/34
CPC分类号： G11C11/22 , G11C29/50
摘要： To implement a high reliability and large number of rewrite operations by optimizing reliability margins of both data “0” and data “1” or a reliability margin of one of the data “0” or data “1” with a circuit for monitoring a rewrite status and a circuit for changing a read condition corresponding to the number of rewrite operations based on a result of monitoring the rewritable status.
摘要翻译：通过利用用于监视重写的电路优化数据“0”和数据“1”的数据“0”或数据“1”之一的可靠性裕度，从而实现高可靠性和大量的重写操作状态和用于基于监视可重写状态的结果来改变与重写操作数相对应的读取条件的电路。

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