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1. 发明申请

US20050260824A1 Semiconductor device manufacturing method and manufacturing line thereof 审中-公开
公开(公告)号：US20050260824A1
公开(公告)日：2005-11-24
申请号：US11189700
申请日：2005-07-27
申请人： Junichi Inoue , Teruo Asakawa , Kazuhiko Sugiyama
发明人： Junichi Inoue , Teruo Asakawa , Kazuhiko Sugiyama
IPC分类号： C23C14/56 , C23C16/54 , H01L21/00 , H01L21/04 , H01L21/76
CPC分类号： H01L21/67225 , C23C14/56 , C23C16/54 , H01L21/0405 , H01L21/67161 , H01L21/67173
摘要： The present invention provides a semiconductor device manufacturing line for applying a series of processes on a semiconductor substrate, and forming an integrated circuit on the semiconductor substrate by employing a semiconductor wafer having a diameter of 6 inches (150±3 mm: SEAJ specification) or less for the semiconductor substrate. This manufacturing line comprises two sub-lines conforming to the same specifications, each of these sub-lines is composed of a series of processing units including a film forming unit, a pattern exposure unit, an etching unit, and a test unit. In at least one pattern exposure unit and one etching unit, fine processing of 0.3 μm or less can be performed.

2. 发明申请

US20050112889A1 Semiconductor device manufacturing method and manufacturing line thereof 失效
标题翻译：半导体装置的制造方法及其制造方法
公开(公告)号：US20050112889A1
公开(公告)日：2005-05-26
申请号：US11024199
申请日：2004-12-29
申请人： Junichi Inoue , Teruo Asakawa , Kazuhiko Sugiyama
发明人： Junichi Inoue , Teruo Asakawa , Kazuhiko Sugiyama
IPC分类号： C23C14/56 , C23C16/54 , H01L21/00 , H01L21/04 , H01L21/66 , G01R31/26 , H01L21/76 , H01L21/302 , H01L21/461
CPC分类号： H01L21/67225 , C23C14/56 , C23C16/54 , H01L21/0405 , H01L21/67161 , H01L21/67173
摘要： The present invention provides a semiconductor device manufacturing line for applying a series of processes on a semiconductor substrate, and forming an integrated circuit on the semiconductor substrate by employing a semiconductor wafer having a diameter of 6 inches (150±3 mm: SEAJ specification) or less for the semiconductor substrate. This manufacturing line comprises two sub-lines conforming to the same specifications, each of these sub-lines is composed of a series of processing units including a film forming unit, a pattern exposure unit, an etching unit, and a test unit. In at least one pattern exposure unit and one etching unit, fine processing of 0.3 μm or less can be performed.
摘要翻译：本发明提供了一种用于在半导体衬底上施加一系列工艺的半导体器件制造线，并且通过采用直径为6英寸（150±3mm：SEAJ规格）的半导体晶片或半导体衬底上形成集成电路，较少用于半导体衬底。该制造线包括符合相同规格的两条子线，这些子线中的每一条由包括成膜单元，图案曝光单元，蚀刻单元和测试单元的一系列处理单元组成。在至少一个图案曝光单元和一个蚀刻单元中，可以执行0.3μm或更小的精细处理。

3. 发明授权

US07566665B2 Semiconductor device manufacturing method and manufacturing line thereof 失效
标题翻译：半导体装置的制造方法及其制造方法
公开(公告)号：US07566665B2
公开(公告)日：2009-07-28
申请号：US11024199
申请日：2004-12-29
申请人： Junichi Inoue , Teruo Asakawa , Kazuhiko Sugiyama
发明人： Junichi Inoue , Teruo Asakawa , Kazuhiko Sugiyama
IPC分类号： H01L21/302
CPC分类号： H01L21/67225 , C23C14/56 , C23C16/54 , H01L21/0405 , H01L21/67161 , H01L21/67173
摘要： The present invention provides a semiconductor device manufacturing line for applying a series of processes on a semiconductor substrate, and forming an integrated circuit on the semiconductor substrate by employing a semiconductor wafer having a diameter of 6 inches (150±3 mm: SEAJ specification) or less for the semiconductor substrate. This manufacturing line comprises two sub-lines conforming to the same specifications, each of these sub-lines is composed of a series of processing units including a film forming unit, a pattern exposure unit, an etching unit, and a test unit. In at least one pattern exposure unit and one etching unit, fine processing of 0.3 μm or less can be performed.
摘要翻译：本发明提供了一种用于在半导体衬底上施加一系列工艺的半导体器件制造线，并且通过采用直径为6英寸（150±3mm：SEAJ规格）的半导体晶片或半导体衬底上形成集成电路，较少用于半导体衬底。该制造线包括符合相同规格的两条子线，这些子线中的每一条由包括成膜单元，图案曝光单元，蚀刻单元和测试单元的一系列处理单元组成。在至少一个图案曝光单元和一个蚀刻单元中，可以执行0.3μm或更小的精细处理。

4. 发明授权

US06841485B1 Method of manufacturing semiconductor device and manufacturing line thereof 失效
标题翻译：制造半导体器件的方法及其制造线
公开(公告)号：US06841485B1
公开(公告)日：2005-01-11
申请号：US09958970
申请日：2000-04-11
申请人： Junichi Inoue , Teruo Asakawa , Kazuhiko Sugiyama
发明人： Junichi Inoue , Teruo Asakawa , Kazuhiko Sugiyama
IPC分类号： C23C14/56 , C23C16/54 , H01L21/00 , H01L21/04 , H01L21/302
CPC分类号： H01L21/67225 , C23C14/56 , C23C16/54 , H01L21/0405 , H01L21/67161 , H01L21/67173
摘要： The present invention provides a semiconductor device manufacturing line for applying a series of processes on a semiconductor substrate, and forming an integrated circuit on the semiconductor substrate by employing a semiconductor wafer having a diameter of 6 inches (150±3 mm: SEAJ specification) or less for the semiconductor substrate. This manufacturing line comprises two sub-lines conforming to the same specifications, each of these sub-lines is composed of a series of processing units including a film forming unit, a pattern exposure unit, an etching unit, and a test unit. In at least one pattern exposure unit and one etching unit, fine processing of 0.3 μm or less can be performed.
摘要翻译：本发明提供了一种用于在半导体衬底上施加一系列工艺的半导体器件制造线，并且通过采用直径为6英寸（150±3mm：SEAJ规格）的半导体晶片或半导体衬底上形成集成电路，较少用于半导体衬底。该制造线包括符合相同规格的两条子线，这些子线中的每一条由包括成膜单元，图案曝光单元，蚀刻单元和测试单元的一系列处理单元组成。在至少一个图案曝光单元和一个蚀刻单元中，可以执行0.3μm或更小的精细处理。

5. 发明申请

US20110085106A1 ALIGNMENT FILM AND METHOD OF MANUFACTURING THE SAME, PHASE DIFFERENCE DEVICE AND METHOD OF MANUFACTURING THE SAME, AND DISPLAY UNIT 有权
标题翻译：对准膜及其制造方法，相位差设备及其制造方法和显示单元
公开(公告)号：US20110085106A1
公开(公告)日：2011-04-14
申请号：US12895993
申请日：2010-10-01
申请人： Kei Obata , Junichi Inoue , Akito Kuriyama , Akihiro Shibata , Kentaroh Ishikawa
发明人： Kei Obata , Junichi Inoue , Akito Kuriyama , Akihiro Shibata , Kentaroh Ishikawa
IPC分类号： G02F1/13357 , G02F1/1335 , B05D5/06 , B05D3/06 , B32B3/30
CPC分类号： G02B5/3016 , G02F1/13363 , Y10T428/1005 , Y10T428/1036 , Y10T428/24537
摘要： An alignment film or a phase difference device with small shift from a desired alignment direction and a display unit including the same are provided. The alignment film includes: a substrate having a plurality of grooves extending in a specific direction on a surface; and a non-alignment thin film formed along a surface of the plurality of grooves. The phase difference device includes: an alignment film that has a substrate having a plurality of grooves extending in a specific direction on a surface and a non-alignment thin film formed along a surface of the plurality of grooves; and a phase difference layer that is provided being contacted with a surface of the non-alignment thin film, and includes a liquid crystal material that is aligned along an extending direction of a dent formed by the non-alignment thin film and is polymerized.
摘要翻译：提供了从期望的取向方向小偏移的取向膜或相位差装置和包括该取向膜的显示单元。取向膜包括：具有在表面上沿特定方向延伸的多个槽的基板; 以及沿多个槽的表面形成的非取向薄膜。所述相位差装置包括：取向膜，其具有基板，所述基板具有沿表面的特定方向延伸的多个槽和沿着所述多个槽的表面形成的非取向薄膜; 所述相位差层与所述非取向薄膜的表面接触，并且包括沿着由所述非取向薄膜形成的凹部的延伸方向排列并被聚合的液晶材料。

6. 发明申请

US20100073604A1 RETARDATION FILM, METHOD OF MANUFACTURING THE SAME, AND DISPLAY 有权
标题翻译：延迟膜，其制造方法和显示
公开(公告)号：US20100073604A1
公开(公告)日：2010-03-25
申请号：US12564505
申请日：2009-09-22
申请人： Kentaro Okuyama , Hitoshi Katakura , Kei Obata , Jun Shimizu , Shinya Suzuki , Mitsunari Hoshi , Junichi Inoue , Akito Kuriyama
发明人： Kentaro Okuyama , Hitoshi Katakura , Kei Obata , Jun Shimizu , Shinya Suzuki , Mitsunari Hoshi , Junichi Inoue , Akito Kuriyama
IPC分类号： G02F1/1347 , G02F1/13 , B29D7/01
CPC分类号： G02B5/3083 , B29D11/00644 , B32B2457/20 , B32B2457/204 , G02B5/045 , G02F1/133555 , G02F1/133636 , G02F2001/133631 , G02F2001/133638 , G02F2202/023 , G02F2413/02 , G02F2413/05 , G02F2413/11
摘要： A retardation film which is manufacturable by a simple process, and being capable of preventing a decline in light use efficiency is provided. A retardation film includes: a substrate having a plurality of grooves extending in a specific direction on a surface thereof; and a retardation layer arranged in contact with the surface of the substrate, and including a liquid crystal material, the liquid crystal material being aligned along the extending direction of the plurality of grooves and being polymerized.
摘要翻译：提供了可以通过简单的工艺制造并且能够防止光利用效率下降的延迟膜。延迟膜包括：具有在其表面上沿特定方向延伸的多个槽的基板; 以及延迟层，与所述基板的表面接触，并且包括液晶材料，所述液晶材料沿着所述多个槽的延伸方向排列并聚合。

7. 发明申请

US20070072637A1 SYSTEM AND METHOD FOR GROUP SESSION COMMUNICATION 审中-公开
标题翻译：用于组会话通信的系统和方法
公开(公告)号：US20070072637A1
公开(公告)日：2007-03-29
申请号：US11533799
申请日：2006-09-21
申请人： Junichi Inoue
发明人： Junichi Inoue
IPC分类号： H04B7/00 , H04Q7/20
CPC分类号： H04W4/08 , H04L65/1093 , H04L65/403 , H04L67/24 , H04L67/26 , H04W4/10 , H04W76/45
摘要： The present invention is directed to a system and method for distributing voice data information as presence information to all members participating in the group session communication when the presence status of participants has changed. A call control server accepts a request from one of group members for joining or exiting the group session communication, and transmits the information on the member to a media control server. The media control server receives the information and extracts media data, from a memory means, corresponding to the received information, and distributes the extracted media data, as voice data, to all participants of the group session communication.
摘要翻译：本发明涉及一种当参与者的存在状态改变时，将语音数据信息作为存在信息分发给参与组会话通信的所有成员的系统和方法。呼叫控制服务器接受来自组成员之一的用于加入或退出组会话通信的请求，并将该成员上的信息发送到媒体控制服务器。媒体控制服务器接收信息并从存储装置中提取对应于接收到的信息的媒体数据，并将提取的媒体数据作为语音数据分发给组会话通信的所有参与者。

8. 发明授权

US5220240A Planar display apparatus 失效
标题翻译：平面显示设备
公开(公告)号：US5220240A
公开(公告)日：1993-06-15
申请号：US631148
申请日：1990-12-20
申请人： Toshio Ohoshi , Akira Nakayama , Junichi Inoue , Masaru Yamaguchi
发明人： Toshio Ohoshi , Akira Nakayama , Junichi Inoue , Masaru Yamaguchi
IPC分类号： H01J31/12
CPC分类号： H01J31/124
摘要： A planar display apparatus with a fluorescent screen formed on the inner surface of a front panel in a planar tube body. An electron gun is disposed at a position deviated in a vertical scanning direction from a region opposite the fluorescent screen, and a vertical deflecting electrode composed of a plurality of parallel electrodes is disposed at an opposite portion relative to the fluorescent screen on the side of a back panel opposed to the front panel of the planar tube body. In a space between the vertical deflecting electrode and the fluorescent screen, there is disposed an electrode structure having at least an electron lens scanning electrode composed of a plurality of parallel electrodes, a splitting electrode for splitting an electron beam from the electron gun into a plurality of beams, a modulating electrode, and horizontal deflection electrodes.

9. 发明授权

US4985378A Carbon-containing refractory and a manufacturing method therefor 失效
$Carbon-containing refractory and a manufacturing method therefor$
标题翻译：含碳耐火材料及其制造方法
公开(公告)号：US4985378A
公开(公告)日：1991-01-15
申请号：US240278
申请日：1988-09-06
申请人： Kenji Ichikawa , Noboru Tsukamoto , Eishi Iida , Yuji Yoshimura , Junichi Inoue
发明人： Kenji Ichikawa , Noboru Tsukamoto , Eishi Iida , Yuji Yoshimura , Junichi Inoue
IPC分类号： B22D11/10 , B22D41/54 , C04B35/00 , C04B35/10 , C04B35/103 , C04B35/64 , C04B35/657 , C04B35/80
CPC分类号： C04B35/10 , C04B35/64 , C04B35/80
摘要： A carbon-containing refractory is formed by mixing 1-10 weight % of silicon nitride, 1-35 weight % of carbon, and a remainder of a refractory raw material, molding the mixture into a molded body, and burning the molded body such that fine whiskers of silicon carbide are uniformly distributed within the matrix.

10. 发明授权

US4835686A Cache system adopting an LRU system, and magnetic disk controller incorporating it 失效
标题翻译：采用LRU系统的缓存系统，以及包含它的磁盘控制器
公开(公告)号：US4835686A
公开(公告)日：1989-05-30
申请号：US867449
申请日：1986-05-28
申请人： Akihiko Furuya , Kouiti Kanamaru , Junichi Inoue
发明人： Akihiko Furuya , Kouiti Kanamaru , Junichi Inoue
IPC分类号： G06F3/06 , G06F11/14 , G06F12/08 , G06F12/12
CPC分类号： G06F3/0601 , G06F12/0866 , G06F12/126 , G06F11/1415 , G06F2003/0691 , G06F2212/312
摘要： A cache system employing an LRU (Least Recently Used) scheme in a replacement algorithm of cache blocks and comprising a directory memory whose entires have LRU counter fields, a host system issuing a read/write command to which an arbitrary LRU setting value is appended, a directory search circuit, and a microprocessor. The directory search circuit searches the directory memory in response to the read/write command issued from the host system. The microprocessor stores the LRU setting value appended to the read/write command in the LRU counter field of the hit entry of the directory memory or of the entry corresponding to the replacement target cache block, in response to the search result of the directory search circuit.

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