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1. 发明授权

US09257444B2 Method of fabricating semiconductor devices having vertical cells 有权
公开(公告)号：US09257444B2
公开(公告)日：2016-02-09
申请号：US14018578
申请日：2013-09-05
申请人： Jung-Ik Oh , Dae-Hyun Jang , Kyoung-Sub Shin
发明人： Jung-Ik Oh , Dae-Hyun Jang , Kyoung-Sub Shin
IPC分类号： H01L21/336 , H01L27/115
CPC分类号： H01L27/11565 , H01L23/528 , H01L27/11573 , H01L27/11575 , H01L27/11582 , H01L2924/0002 , H01L2924/00
摘要： According to example embodiments, a method of fabricating a semiconductor device includes: forming a preliminary stack structure including upper and lower preliminary stack structures by alternately stacking a plurality of interlayer insulating and sacrificial layers on a cell, first pad area, dummy area and second pad area of a substrate; removing an entire portion of the upper preliminary stack structure on the second pad area; forming a first mask defining openings over parts of the first and second pad areas; etching an etch depth corresponding to ones of the plurality of interlayer insulating and sacrificial layers through a remaining part of the preliminary stack structure exposed by the first mask; and repetitively performing a first staircase forming process that includes shrinking sides of the first mask and etching the etch depth through remaining parts of the plurality of interlayer insulating and sacrificial layers exposed by the shrunken first mask.

2. 发明授权

US09419008B2 Method of fabricating semiconductor devices having vertical cells 有权
标题翻译：制造具有垂直单元的半导体器件的方法
公开(公告)号：US09419008B2
公开(公告)日：2016-08-16
申请号：US14795352
申请日：2015-07-09
申请人： Jung-Ik Oh , Dae-Hyun Jang , Kyoung-Sub Shin
发明人： Jung-Ik Oh , Dae-Hyun Jang , Kyoung-Sub Shin
IPC分类号： H01L27/115 , H01L23/528
CPC分类号： H01L27/11565 , H01L23/528 , H01L27/11573 , H01L27/11575 , H01L27/11582 , H01L2924/0002 , H01L2924/00
摘要： According to example embodiments, a method of fabricating a semiconductor device includes: forming a preliminary stack structure including upper and lower preliminary stack structures by alternately stacking a plurality of interlayer insulating and sacrificial layers on a cell, first pad area, dummy area and second pad area of a substrate; removing an entire portion of the upper preliminary stack structure on the second pad area; forming a first mask defining openings over parts of the first and second pad areas; etching an etch depth corresponding to ones of the plurality of interlayer insulating and sacrificial layers through a remaining part of the preliminary stack structure exposed by the first mask; and repetitively performing a first staircase forming process that includes shrinking sides of the first mask and etching the etch depth through remaining parts of the plurality of interlayer insulating and sacrificial layers exposed by the shrunken first mask.
摘要翻译：根据示例性实施例，制造半导体器件的方法包括：通过在单元，第一焊盘区域，虚拟区域和第二焊盘上交替堆叠多个层间绝缘和牺牲层来形成包括上部和下部初级堆叠结构的预备叠层结构基材面积; 去除所述第二焊盘区域上的所述上部初级堆叠结构的整个部分; 形成在所述第一和第二焊盘区域的部分上限定开口的第一掩模; 通过由第一掩模曝光的预备叠层结构的剩余部分来蚀刻对应于多个层间绝缘层和牺牲层中的一个的蚀刻深度; 并且重复地进行第一阶梯形成处理，其包括收缩第一掩模的侧面并通过由缩小的第一掩模暴露的多个层间绝缘和牺牲层的剩余部分蚀刻蚀刻深度。

3. 发明授权

US09048193B2 Method of forming a step pattern structure 有权
标题翻译：形成台阶图案结构的方法
公开(公告)号：US09048193B2
公开(公告)日：2015-06-02
申请号：US13910734
申请日：2013-06-05
申请人： Jung-Ik Oh , Dae-Hyun Jang , Seong-Soo Lee , Han-Na Cho
发明人： Jung-Ik Oh , Dae-Hyun Jang , Seong-Soo Lee , Han-Na Cho
IPC分类号： H01L21/44 , H01L21/308 , H01L21/768 , H01L21/311 , H01L27/115 , H01L21/027
CPC分类号： H01L21/308 , H01L21/0273 , H01L21/31144 , H01L21/76838 , H01L21/76885 , H01L27/11575 , H01L27/11582
摘要： A method of forming a multi-floor step pattern structure includes forming a stacked structure having alternating insulating interlayers and sacrificial layers on a substrate. A first photoresist pattern is formed on the stacked structure. A first preliminary step pattern structure is formed by etching portions of the stacked structure using the first photoresist pattern as an etching mask. A passivation layer pattern is formed on upper surfaces of the first photoresist pattern and the first preliminary step pattern structure. A second photoresist pattern is formed by removing a side wall portion of the first photoresist pattern exposed by the passivation layer pattern. A second preliminary step pattern structure is formed by etching exposed insulating interlayers and underlying sacrificial layers using the second photoresist pattern as an etching mask. The above steps may be repeated on the second preliminary step pattern structure to form the multi-floor step pattern structure.
摘要翻译：形成多层台阶图案结构的方法包括在基板上形成具有交替的绝缘夹层和牺牲层的堆叠结构。第一光致抗蚀剂图案形成在堆叠结构上。通过使用第一光致抗蚀剂图案作为蚀刻掩模蚀刻层叠结构的部分来形成第一预备步骤图案结构。钝化层图案形成在第一光致抗蚀剂图案和第一初步步骤图案结构的上表面上。通过去除由钝化层图案暴露的第一光致抗蚀剂图案的侧壁部分形成第二光致抗蚀剂图案。通过使用第二光致抗蚀剂图案作为蚀刻掩模蚀刻暴露的绝缘夹层和下面的牺牲层来形成第二初步步骤图案结构。可以在第二预备步骤图案结构上重复上述步骤以形成多层台阶图案结构。

4. 发明授权

US09543307B2 Vertical memory devices and methods of manufacturing the same 有权
标题翻译：垂直存储器件及其制造方法
公开(公告)号：US09543307B2
公开(公告)日：2017-01-10
申请号：US14792114
申请日：2015-07-06
申请人： Ha-Na Kim , Dae-Hyun Jang , Jung-Ik Oh
发明人： Ha-Na Kim , Dae-Hyun Jang , Jung-Ik Oh
IPC分类号： H01L21/02 , H01L21/48 , H01L27/105 , H01L27/02
CPC分类号： H01L27/1052 , H01L21/481 , H01L21/4846 , H01L21/486 , H01L27/0207 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L27/11582
摘要： A method of manufacturing a vertical memory device includes: providing a substrate including a cell array region and a peripheral circuit region; forming a mold structure in the cell array region; forming a mold protection film in a portion of the cell array region and the peripheral circuit region, the mold protection film contacting the mold structure; forming an opening for a common source line that passes through the mold structure and extends in a first direction perpendicular to a top surface of the substrate; forming a peripheral circuit contact hole that passes through the mold protection film and extends in the first direction in the peripheral circuit region; and simultaneously forming a first contact plug and a second contact plug, respectively, in the opening for the common source line and in the peripheral circuit contact hole.
摘要翻译：制造垂直存储器件的方法包括：提供包括单元阵列区域和外围电路区域的衬底; 在电池阵列区域中形成模具结构; 在电池阵列区域和外围电路区域的一部分中形成保护膜，模具保护膜与模具结构接触; 形成用于通过所述模具结构并沿垂直于所述基板的顶表面的第一方向延伸的共同源极线的开口; 形成通过所述保护膜并在所述外围电路区域沿所述第一方向延伸的外围电路接触孔; 同时在公共源极线的开口和外围电路接触孔中分别形成第一接触插塞和第二接触插塞。

5. 发明授权

US09455268B2 Staircase-shaped connection structures of three-dimensional semiconductor devices 有权
标题翻译：三维半导体器件的阶梯状连接结构
公开(公告)号：US09455268B2
公开(公告)日：2016-09-27
申请号：US14520751
申请日：2014-10-22
申请人： Jung-Ik Oh , Daehyun Jang , Ha-Na Kim , Kyoungsub Shin
发明人： Jung-Ik Oh , Daehyun Jang , Ha-Na Kim , Kyoungsub Shin
IPC分类号： H01L25/00 , H01L27/11 , H01L45/00 , H01L27/115 , H01L25/065
CPC分类号： H01L21/0274 , H01L21/30604 , H01L21/3085 , H01L25/0657 , H01L25/50 , H01L27/11521 , H01L27/11556 , H01L27/11575 , H01L27/11582 , H01L27/2481 , H01L45/122 , H01L45/1253 , H01L2924/0002 , H01L2924/00
摘要： Provided is a staircase-shaped connection structure of a three-dimensional semiconductor device. The device includes an electrode structure on a substrate, the electrode structure including an upper staircase region, a lower staircase region, and a buffer region therebetween. The electrode structure includes horizontal electrodes sequentially stacked on the substrate, the horizontal electrodes include a plurality of pad regions constituting a staircase structure of each of the upper and lower staircase regions, and the buffer region has a width that is larger than that of each of the pad regions.
摘要翻译：提供了三维半导体器件的阶梯状连接结构。该装置包括在基板上的电极结构，电极结构包括上层阶段区域，下层阶梯区域和它们之间的缓冲区域。电极结构包括依次堆叠在基板上的水平电极，水平电极包括构成上下阶梯区域中的每一个的阶梯结构的多个焊盘区域，并且缓冲区域的宽度大于垫区域。

6. 发明授权

US09608040B2 Memory device and method of fabricating the same 有权
公开(公告)号：US09608040B2
公开(公告)日：2017-03-28
申请号：US15158981
申请日：2016-05-19
申请人： Gwang-Hyun Baek , Inho Kim , Jong-Kyu Kim , Jongchul Park , Jung-Ik Oh
发明人： Gwang-Hyun Baek , Inho Kim , Jong-Kyu Kim , Jongchul Park , Jung-Ik Oh
IPC分类号： H01L43/12 , H01L27/22 , H01L43/02 , H01L43/08 , H01L43/10 , G11C11/16 , H01L23/528
CPC分类号： H01L27/228 , G11C11/161 , H01L23/528 , H01L27/226 , H01L43/02 , H01L43/08 , H01L43/10 , H01L43/12
摘要： A memory device including a substrate, an insulating layer on the substrate, the insulating layer including a first region having a first top surface and a second region having a second top surface, the second top surface being lower than the first top surface with respect to the substrate, the first region including a first through hole penetrating therethrough, the second region including a second through hole penetrating therethrough, a first conductive pattern filling the first through hole, a second conductive pattern at least partially filling the second through hole, a magnetic tunnel junction pattern on the first conductive pattern, and a contact plug coupled to the second conductive pattern may be provided. Further, a method of fabricating the memory device also may be provided.

7. 发明授权

US09087790B2 Method of fabricating three-dimensional semiconductor device and three-dimensional semiconductor device fabricated using the same 有权
标题翻译：制造三维半导体器件的方法和使用其制造的三维半导体器件
公开(公告)号：US09087790B2
公开(公告)日：2015-07-21
申请号：US13949600
申请日：2013-07-24
申请人： Jung-Ik Oh , Daehyun Jang , Ha-Na Kim , Seongsoo Lee
发明人： Jung-Ik Oh , Daehyun Jang , Ha-Na Kim , Seongsoo Lee
IPC分类号： H01L21/311 , H01L21/308 , H01L27/115
CPC分类号： H01L21/308 , H01L21/31144 , H01L27/11529 , H01L27/11548 , H01L27/11556 , H01L27/11573 , H01L27/11575 , H01L27/11582
摘要： According to example embodiments of inventive concepts, a method of fabricating a 3D semiconductor device may include: forming a stack structure including a plurality of horizontal layers sequentially stacked on a substrate including a cell array region and a contact region; forming a first mask pattern covering the cell array region and defining openings extending in one direction over the contact region; performing a first etching process with a first etch-depth using the first mask pattern as an etch mask on the stack structure; forming a second mask pattern covering the cell array region and exposing a part of the contact region; and performing a second etching process with a second etch-depth using the second mask pattern as an etch mask structure on the stack structure. The second etch-depth may be greater than the first etch-depth.
摘要翻译：根据发明构思的示例性实施例，制造3D半导体器件的方法可以包括：形成包括依次层叠在包括单元阵列区域和接触区域的基板上的多个水平层的堆叠结构; 形成覆盖所述单元阵列区域并限定在所述接触区域上沿一个方向延伸的开口的第一掩模图案; 使用所述第一掩模图案作为所述堆叠结构上的蚀刻掩模，利用第一蚀刻深度执行第一蚀刻工艺; 形成覆盖所述单元阵列区域并露出所述接触区域的一部分的第二掩模图案; 以及使用所述第二掩模图案作为所述堆叠结构上的蚀刻掩模结构，用第二蚀刻深度执行第二蚀刻工艺。第二蚀刻深度可以大于第一蚀刻深度。

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