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1. 发明授权

US06218208B1 Fabrication of a multi-structure ion sensitive field effect transistor with a pH sensing layer of a tin oxide thin film 有权
标题翻译：制造具有氧化锡薄膜的pH感应层的多结构离子敏感场效应晶体管
公开(公告)号：US06218208B1
公开(公告)日：2001-04-17
申请号：US09347226
申请日：1999-07-02
申请人： Jung-Chuan Chou , Wen-Yaw Chung , Shen-Kan Hsiung , Tai-Ping Sun , Hung-Kwei Liao
发明人： Jung-Chuan Chou , Wen-Yaw Chung , Shen-Kan Hsiung , Tai-Ping Sun , Hung-Kwei Liao
IPC分类号： H01L2100
CPC分类号： G01N27/414
摘要： A sensitive material-tin oxide (SnO2) obtained by thermal evaporation or by r.f. reactive sputtering is used as a high-pH-sensitive material for a Multi-Structure Ion Sensitive Field Effect Transistor. The multi-structure of this Ion Sensitive Field Effect Transistor (ISFET) includes SnO2/SiO2 gate ISFET or SnO2/Si3N4/SiO2 gate ISFET respectively, and which have high performances such as a linear pH sensitivity of approximately 56˜58 mV/pH in a concentration range between pH2 and pH10. A low drift characteristics of approximately 5 mv/day, response time is less than 0.1 second, and an isothermal point of this ISFET sensor can be obtained if the device operates with an adequate drain-source current. In addition, this invention has other advantages, such as the inexpensive fabrication system, low cost, and mass production characteristics. Based on these characteristics, a disposal sensing device can be achieved. Thus, this invention has a high feasibility in Ion Sensitive Field Effect Transistor.
摘要翻译：通过热蒸发或r.f.获得的敏感材料 - 氧化锡（SnO 2）。反应溅射用作多结构离子敏感场效应晶体管的高pH敏感材料。该离子敏感场效应晶体管（ISFET）的多结构分别包括SnO 2 / SiO 2栅极ISFET或SnO 2 / Si 3 N 4 / SiO 2栅极ISFET，并且具有高性能，例如约56〜58mV / pH的线性pH灵敏度 pH2和pH10之间的浓度范围。大约5mv /天的低漂移特性，响应时间小于0.1秒，如果器件以足够的漏源电流工作，则可以获得该ISFET传感器的等温点。此外，本发明还具有廉价的制造系统，低成本和批量生产特性等其它优点。基于这些特性，可以实现处置感测装置。因此，本发明在离子敏感场效应晶体管中具有很高的可行性。

2. 发明授权

US06236075B1 Ion sensitive transistor 有权
标题翻译：离子敏感晶体管
公开(公告)号：US06236075B1
公开(公告)日：2001-05-22
申请号：US09266420
申请日：1999-03-10
申请人： Shen-Kan Hsiung , Jung-Chuan Chou , Tai-Ping Sun , Wen Yaw Chung , Hung-Kwei Liao , Chung-Lin Wu
发明人： Shen-Kan Hsiung , Jung-Chuan Chou , Tai-Ping Sun , Wen Yaw Chung , Hung-Kwei Liao , Chung-Lin Wu
IPC分类号： H01L2358
CPC分类号： G01N27/414
摘要： The present invention discloses a method of forming a metal layer by thermal evaporation or RF reactive sputtering in order to fabricate a light shielding layer for an ion sensitive field effect transistor. The multi-layered construction of the ion sensitive field effect transistor with a metal thin film as a light shielding layer is SnO2/metal/SiO2 or SnO2/metal/Si3N4/SiO2, and is able to lower the effect of light successfully.
摘要翻译：本发明公开了一种通过热蒸镀或RF反应溅射形成金属层的方法，以制造用于离子敏感场效应晶体管的遮光层。具有金属薄膜作为遮光层的离子敏感场效应晶体管的多层结构是SnO 2 /金属/ SiO 2或SnO 2 /金属/ Si 3 N 4 / SiO 2，并且能够成功地降低光的效果。

3. 发明授权

US06734106B2 Method of buried strap out-diffusion formation by gas phase doping 有权
标题翻译：通过气相掺杂掩埋带外扩散形成的方法
公开(公告)号：US06734106B2
公开(公告)日：2004-05-11
申请号：US10195355
申请日：2002-07-15
申请人： Jesse Chung , Hsio-Lei Wang , Hung-Kwei Liao
发明人： Jesse Chung , Hsio-Lei Wang , Hung-Kwei Liao
IPC分类号： H01L21302
CPC分类号： H01L27/10867 , H01L21/743
摘要： A method of forming a buried strap comprising the following sequential steps. A substrate having a pad oxide layer formed thereover is provided. A masking layer is formed over the pad oxide layer. The masking layer, pad oxide layer and substrate are etched to form a trench within the substrate. The trench having an outer sidewall and an upper portion. The upper portion of the trench is lined with a collar. A poly plate is formed within the trench. The poly plate and collar are etched below the substrate to form a recessed poly plate and a recessed collar and exposing a portion of outer sidewall of trench. Ions are implanted into the substrate through exposed outer sidewall of trench by gas phase doping. A SiN sidewall layer is formed over the exposed outer sidewall of trench at a temperature sufficient to diffuse the implanted ions further into the substrate to form the buried strap.
摘要翻译：一种形成掩埋带的方法，包括以下顺序步骤。提供了具有形成在其上的衬垫氧化物层的衬底。在衬垫氧化物层上形成掩模层。蚀刻掩模层，衬垫氧化物层和衬底以在衬底内形成沟槽。沟槽具有外侧壁和上部。沟槽的上部衬有一个领。在沟槽内形成多晶硅板。多晶板和套环被蚀刻在基底下方以形成凹入的多晶硅板和凹入的套环，并暴露沟槽外侧壁的一部分。通过气相掺杂，通过暴露的沟槽的外侧壁将离子注入到衬底中。在足以将注入的离子进一步扩散到衬底中以形成掩埋带的温度下，在沟槽的暴露的外侧壁上形成SiN侧壁层。

4. 发明申请

US20070052008A1 Memory structure with high coupling ratio 有权
标题翻译：高耦合比的记忆体结构
公开(公告)号：US20070052008A1
公开(公告)日：2007-03-08
申请号：US11272683
申请日：2005-11-15
申请人： Chih-Ping Chung , Chun-Nan Lin , Chung-Yi Chen , Hung-Kwei Liao
发明人： Chih-Ping Chung , Chun-Nan Lin , Chung-Yi Chen , Hung-Kwei Liao
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/42324 , H01L21/28273
摘要： A memory structure comprising a plurality of memory cells is described. Each memory cell comprises a substrate, a shallow trench isolation, a spacer, a tunnel oxide, and a floating gate. The shallow trench isolation in the substrate is used to define an active area. The spacer is at the sidewall of the shallow trench isolation and is higher than the shallow trench isolation. The tunnel oxide is on the active area. The floating gate is on the tunnel oxide.
摘要翻译：描述包括多个存储器单元的存储器结构。每个存储单元包括衬底，浅沟槽隔离，间隔物，隧道氧化物和浮动栅极。衬底中的浅沟槽隔离用于限定有源区。间隔物位于浅沟槽隔离物的侧壁处，并且高于浅沟槽隔离。隧道氧化物在有源区上。浮动栅极在隧道氧化物上。

5. 发明授权

US07427569B2 Metal etching process and rework method thereof 有权
标题翻译：金属蚀刻工艺及其返工方法
公开(公告)号：US07427569B2
公开(公告)日：2008-09-23
申请号：US11307801
申请日：2006-02-23
申请人： Tza-Hao Wang , Jin-Yang Huang , Hung-Kwei Liao , Ming-Sheng Tung
发明人： Tza-Hao Wang , Jin-Yang Huang , Hung-Kwei Liao , Ming-Sheng Tung
IPC分类号： H01L21/00 , H01L21/302 , H01L21/461
CPC分类号： H01L21/32139 , H01L21/321 , H01L21/32135
摘要： A metal etching process is described. A substrate having a dielectric layer thereon is provided. An aluminum-copper alloy layer is formed on the dielectric layer. A hard mask layer is formed on the aluminum-copper alloy layer. A patterned photoresist layer is formed on the hard mask layer and then the hard mask layer is patterned. A thermal treatment process is performed. The thermal treatment process is carried out at a temperature of more than 300° C. for a period of at least 3 minutes. Thereafter, the aluminum-copper alloy layer is etched using the patterned hard mask layer as an etching mask. Due to the thermal treatment, the metal precipitate (CuAl2) within the aluminum-copper alloy layer is eliminated and hence the metal etching process is improved.
摘要翻译：描述金属蚀刻工艺。提供其上具有介电层的基板。在电介质层上形成铝 - 铜合金层。在铝 - 铜合金层上形成硬掩模层。在硬掩模层上形成图案化的光致抗蚀剂层，然后对硬掩模层进行图案化。进行热处理工艺。热处理过程在大于300℃的温度下进行至少3分钟的时间。此后，使用图案化的硬掩模层作为蚀刻掩模蚀刻铝 - 铜合金层。由于热处理，铝 - 铜合金层内的金属沉淀物（CuAl 2 N 2）被消除，因此改善了金属蚀刻工艺。

6. 发明申请

US20070166979A1 METAL ETCHING PROCESS AND REWORK METHOD THEREOF 有权
标题翻译：金属蚀刻工艺及其制作方法
公开(公告)号：US20070166979A1
公开(公告)日：2007-07-19
申请号：US11307801
申请日：2006-02-23
申请人： Tza-Hao Wang , Jin-Yang Huang , Hung-Kwei Liao , Ming-Sheng Tung
发明人： Tza-Hao Wang , Jin-Yang Huang , Hung-Kwei Liao , Ming-Sheng Tung
IPC分类号： H01L21/44
CPC分类号： H01L21/32139 , H01L21/321 , H01L21/32135
摘要： A metal etching process is described. A substrate having a dielectric layer thereon is provided. An aluminum-copper alloy layer is formed on the dielectric layer. A hard mask layer is formed on the aluminum-copper alloy layer. A patterned photoresist layer is formed on the hard mask layer and then the hard mask layer is patterned. A thermal treatment process is performed. The thermal treatment process is carried out at a temperature of more than 300° C. for a period of at least 3 minutes. Thereafter, the aluminum-copper alloy layer is etched using the patterned hard mask layer as an etching mask. Due to the thermal treatment, the metal precipitate (CuAl2) within the aluminum-copper alloy layer is eliminated and hence the metal etching process is improved.
摘要翻译：描述金属蚀刻工艺。提供其上具有介电层的基板。在电介质层上形成铝 - 铜合金层。在铝 - 铜合金层上形成硬掩模层。在硬掩模层上形成图案化的光致抗蚀剂层，然后对硬掩模层进行图案化。进行热处理工艺。热处理过程在大于300℃的温度下进行至少3分钟的时间。此后，使用图案化的硬掩模层作为蚀刻掩模蚀刻铝 - 铜合金层。由于热处理，铝 - 铜合金层内的金属沉淀物（CuAl 2 N 2）被消除，因此改善了金属蚀刻工艺。

7. 发明授权

US07485917B2 Split gate flash memory cell and fabrication method thereof 有权
标题翻译：分离式闪存单元及其制造方法
公开(公告)号：US07485917B2
公开(公告)日：2009-02-03
申请号：US11390144
申请日：2006-03-28
申请人： Ching-Hung Fu , Hung-Kwei Liao , Chien-Chung Lu
发明人： Ching-Hung Fu , Hung-Kwei Liao , Chien-Chung Lu
IPC分类号： H01L29/788
CPC分类号： H01L29/7886 , H01L21/28273 , H01L29/42328
摘要： A split gate flash memory cell comprising a semiconductor substrate having a first insulating layer thereon and a floating gate with a first width is disclosed. The cell further comprises a second insulating layer, a control gate and a cap on the floating gate in sequence. The cap layer, the control gate and the second insulating layer have a same second width less than the first width. The cell also comprises a third insulating layer over the semiconductor substrate, the sidewalls of the control gate, the second insulating layer, the floating gate, and the first insulating layer. In addition, an erase gate formed on the third insulating layer is provided.
摘要翻译：公开了一种分离栅闪存单元，其包括其上具有第一绝缘层的半导体衬底和具有第一宽度的浮动栅极。电池还依次包括浮置栅极上的第二绝缘层，控制栅极和盖子。盖层，控制栅极和第二绝缘层具有小于第一宽度的相同的第二宽度。电池还包括半导体衬底上的第三绝缘层，控制栅极的侧壁，第二绝缘层，浮置栅极和第一绝缘层。此外，设置形成在第三绝缘层上的擦除栅极。

8. 发明申请

US20080102577A1 Method for Preparing a Trench Capacitor Structure 审中-公开
标题翻译：制备沟槽电容器结构的方法
公开(公告)号：US20080102577A1
公开(公告)日：2008-05-01
申请号：US11564191
申请日：2006-11-28
申请人： Su Chen Lai , Hung-Kwei Liao
发明人： Su Chen Lai , Hung-Kwei Liao
IPC分类号： H01L21/8242
CPC分类号： H01L29/66181 , H01L27/1087
摘要： A method for preparing a trench capacitor structure first forms at least one trench in a substrate, and forms a buried bottom electrode on the lower outer surface of the trench. A dielectric layer is formed to cover an inner sidewall of the trench, and a plurality of deposition processes are then performed to form several polysilicon layers in the trench, wherein a process of introducing a gas containing dopants into the trench is performed at an interval of these deposition processes to diffuse the dopants into the polysilicon layers. Afterward, a planarization process and an anisotropic dry etching process are performed to remove a portion of the polysilicon layers from the top portion of the trench to form a top electrode in the lower portion of the trench. A collar insulation layer is then formed on the upper sidewall of the trench, and the collar insulation layer is used as an implanting mask to perform an implanting process to implant the dopants into the top electrode.
摘要翻译：用于制备沟槽电容器结构的方法首先在衬底中形成至少一个沟槽，并且在沟槽的下外表面上形成掩埋底电极。形成介电层以覆盖沟槽的内侧壁，然后执行多个沉积工艺以在沟槽中形成多个多晶硅层，其中将以含有掺杂剂的气体引入沟槽的过程以这些沉积工艺将掺杂剂扩散到多晶硅层中。之后，进行平面化处理和各向异性干蚀刻处理，以从沟槽的顶部去除一部分多晶硅层，以在沟槽的下部形成顶部电极。然后在沟槽的上侧壁上形成套环绝缘层，并且使用套环绝缘层作为注入掩模来执行注入工艺以将掺杂剂注入到顶部电极中。

9. 发明申请

US20070093024A1 Split gate flash memory cell and fabrication method thereof 有权
标题翻译：分离式闪存单元及其制造方法
公开(公告)号：US20070093024A1
公开(公告)日：2007-04-26
申请号：US11390144
申请日：2006-03-28
申请人： Ching-Hung Fu , Hung-Kwei Liao , Chien-Chung Lu
发明人： Ching-Hung Fu , Hung-Kwei Liao , Chien-Chung Lu
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L29/7886 , H01L21/28273 , H01L29/42328
摘要： A split gate flash memory cell comprising a semiconductor substrate having a first insulating layer thereon and a floating gate with a first width is disclosed. The cell further comprises a second insulating layer, a control gate and a cap on the floating gate in sequence. The cap layer, the control gate and the second insulating layer have a same second width less than the first width. The cell also comprises a third insulating layer over the semiconductor substrate, the sidewalls of the control gate, the second insulating layer, the floating gate, and the first insulating layer. In addition, an erase gate formed on the third insulating layer is provided.
摘要翻译：公开了一种分离栅闪存单元，其包括其上具有第一绝缘层的半导体衬底和具有第一宽度的浮动栅极。电池还依次包括浮置栅极上的第二绝缘层，控制栅极和盖子。盖层，控制栅极和第二绝缘层具有小于第一宽度的相同的第二宽度。电池还包括半导体衬底上的第三绝缘层，控制栅极的侧壁，第二绝缘层，浮置栅极和第一绝缘层。此外，设置形成在第三绝缘层上的擦除栅极。

10. 发明申请

US20070052003A1 Method for producing a memory with high coupling ratio 审中-公开
标题翻译：具有高耦合比的存储器的制造方法
公开(公告)号：US20070052003A1
公开(公告)日：2007-03-08
申请号：US11272685
申请日：2005-11-15
申请人： Chih-Ping Chung , Chun-Nan Lin , Chung-Yi Chen , Hung-Kwei Liao
发明人： Chih-Ping Chung , Chun-Nan Lin , Chung-Yi Chen , Hung-Kwei Liao
IPC分类号： H01L21/336
CPC分类号： H01L29/42324 , H01L29/40114
摘要： A method for producing a memory with high coupling ratio is provided. First, a shallow trench isolation is formed on a substrate to define an active area. Second, a spacer is formed at the sidewall of the shallow trench isolation. Third, the shallow trench isolation is etched such that the top of the spacer is higher than the surface of the shallow trench isolation. Fourth, a tunnel oxide is formed on the active area. Finally, a floating gate is formed on the tunnel oxide.
摘要翻译：提供了一种制造具有高耦合比的存储器的方法。首先，在衬底上形成浅沟槽隔离以限定有源区域。第二，在浅沟槽隔离物的侧壁处形成间隔物。第三，浅沟槽隔离被蚀刻，使得间隔物的顶部高于浅沟槽隔离的表面。第四，在有源区上形成隧道氧化物。最后，在隧道氧化物上形成浮栅。

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