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1. 发明授权

US07851350B2 Semiconductor device and method of forming contact plug of semiconductor device 有权
标题翻译：形成半导体器件接触插塞的半导体器件及方法
公开(公告)号：US07851350B2
公开(公告)日：2010-12-14
申请号：US11965368
申请日：2007-12-27
申请人： Whee Won Cho , Jung Geun Kim , Eun Soo Kim
发明人： Whee Won Cho , Jung Geun Kim , Eun Soo Kim
IPC分类号： H01L21/4763
CPC分类号： H01L21/76804 , H01L21/76831
摘要： The present invention relates to a semiconductor device and a method of forming a contact plug of a semiconductor device. According to the method, a first dielectric layer is formed on a semiconductor substrate in which junction regions are formed. A hard mask is formed on the first dielectric layer. The hard mask and the first dielectric layer corresponding to the junction regions are etched to form trenches. Spacers are formed on sidewalls of the trenches. Contact holes are formed in the first dielectric layer using an etch process employing the spacers and the hard mask so that the junction regions are exposed. The contact holes are gap filled with a conductive material, thus forming contact plugs. Accordingly, bit lines can be easily formed on the contact plugs formed at narrow spaces with a high density.
摘要翻译：本发明涉及半导体器件和形成半导体器件的接触插塞的方法。根据该方法，在形成有接合区域的半导体基板上形成第一电介质层。在第一电介质层上形成硬掩模。对应于接合区域的硬掩模和第一介电层被蚀刻以形成沟槽。间隙形成在沟槽的侧壁上。使用使用间隔物和硬掩模的蚀刻工艺在第一介电层中形成接触孔，使得接合区域露出。接触孔用导电材料间隙填充，从而形成接触塞。因此，可以容易地在高密度的狭窄空间形成的接触塞上形成位线。

2. 发明授权

US08692376B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08692376B2
公开(公告)日：2014-04-08
申请号：US13463071
申请日：2012-05-03
申请人： Jung Geun Kim , Whee Won Cho , Eun Soo Kim
发明人： Jung Geun Kim , Whee Won Cho , Eun Soo Kim
IPC分类号： H01L23/48
CPC分类号： H01L21/76883 , H01L21/3215 , H01L21/76825
摘要： A method of manufacturing a semiconductor device includes forming an interlayer dielectric layer, forming trenches by etching the interlayer dielectric layer, forming a copper (Cu) layer to fill the trenches, and implanting at least one of an inert element, a nonmetallic element, and a metallic element onto a surface of the Cu layer.
摘要翻译：一种制造半导体器件的方法包括形成层间电介质层，通过蚀刻层间电介质层形成沟槽，形成铜（Cu）层以填充沟槽，以及注入惰性元素，非金属元素和在Cu层的表面上的金属元素。

3. 发明申请

US20120280397A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120280397A1
公开(公告)日：2012-11-08
申请号：US13463071
申请日：2012-05-03
申请人： Jung Geun KIM , Whee Won Cho , Eun Soo Kim
发明人： Jung Geun KIM , Whee Won Cho , Eun Soo Kim
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/76883 , H01L21/3215 , H01L21/76825
摘要： A method of manufacturing a semiconductor device includes forming an interlayer dielectric layer, forming trenches by etching the interlayer dielectric layer, forming a copper (Cu) layer to fill the trenches, and implanting at least one of an inert element, a nonmetallic element, and a metallic element onto a surface of the Cu layer.
摘要翻译：一种制造半导体器件的方法包括形成层间电介质层，通过蚀刻层间电介质层形成沟槽，形成铜（Cu）层以填充沟槽，以及注入惰性元素，非金属元素和在Cu层的表面上的金属元素。

4. 发明授权

US07977205B2 Method of forming isolation layer of semiconductor device 失效
标题翻译：形成半导体器件隔离层的方法
公开(公告)号：US07977205B2
公开(公告)日：2011-07-12
申请号：US12815317
申请日：2010-06-14
申请人： Cha Deok Dong , Whee Won Cho , Jung Geun Kim , Cheol Mo Jeong , Suk Joong Kim , Jung Gu Lee
发明人： Cha Deok Dong , Whee Won Cho , Jung Geun Kim , Cheol Mo Jeong , Suk Joong Kim , Jung Gu Lee
IPC分类号： H01L21/76
CPC分类号： H01L27/11521 , H01L21/76232
摘要： A method of forming an isolation layer of a semiconductor device includes forming first trenches in an isolation region of a semiconductor substrate. Sidewalls and a bottom surface of each of the first trenches are oxidized by a radical oxidization process to form a first oxide layer. An oxidization-prevention spacer is formed on the sidewalls of each of the first trenches. Second trenches are formed in the isolation region below the corresponding first trenches, wherein each second trench is narrower and deeper than the corresponding first trench. The second trenches are filled with a second oxide layer. The first trenches are filled with an insulating layer.
摘要翻译：形成半导体器件的隔离层的方法包括在半导体衬底的隔离区域中形成第一沟槽。每个第一沟槽的侧壁和底表面被自由基氧化过程氧化以形成第一氧化物层。在每个第一沟槽的侧壁上形成防氧化间隔物。第二沟槽形成在对应的第一沟槽下方的隔离区域中，其中每个第二沟槽比相应的第一沟槽更窄和更深。第二沟槽填充有第二氧化物层。第一沟槽填充有绝缘层。

5. 发明授权

US07736991B2 Method of forming isolation layer of semiconductor device 失效
标题翻译：形成半导体器件隔离层的方法
公开(公告)号：US07736991B2
公开(公告)日：2010-06-15
申请号：US11617690
申请日：2006-12-28
申请人： Cha Deok Dong , Whee Won Cho , Jung Geun Kim , Cheol Mo Jeong , Suk Joong Kim , Jung Gu Lee
发明人： Cha Deok Dong , Whee Won Cho , Jung Geun Kim , Cheol Mo Jeong , Suk Joong Kim , Jung Gu Lee
IPC分类号： H01L21/76
CPC分类号： H01L27/11521 , H01L21/76232
摘要： A method of forming an isolation layer of a semiconductor device includes forming first trenches in an isolation region of a semiconductor substrate. A spacer is formed on sidewalls of each of the first trenches. Second trenches are formed in the isolation region below the corresponding first trenches. Each second trench is narrower and deeper than the corresponding first trench. A first oxide layer is formed on sidewalls and a bottom surface of each of the second trenches. The first trench is filled with an insulating layer.
摘要翻译：形成半导体器件的隔离层的方法包括在半导体衬底的隔离区域中形成第一沟槽。间隔件形成在每个第一沟槽的侧壁上。第二沟槽形成在对应的第一沟槽下方的隔离区域中。每个第二沟槽比相应的第一沟槽更窄和更深。第一氧化物层形成在每个第二沟槽的侧壁和底表面上。第一沟槽填充有绝缘层。

6. 发明申请

US20080003796A1 METHOD OF FORMING BIT LINE OF SEMICONDUCTOR DEVICE 有权
标题翻译：形成半导体器件位线的方法
公开(公告)号：US20080003796A1
公开(公告)日：2008-01-03
申请号：US11614082
申请日：2006-12-21
申请人： Cheol Mo JEONG , Whee Won Cho , Eun Soo Kim , Seung Hee Hong
发明人： Cheol Mo JEONG , Whee Won Cho , Eun Soo Kim , Seung Hee Hong
IPC分类号： H01L21/44
CPC分类号： H01L21/76864 , H01L21/28562 , H01L21/28568 , H01L21/76846 , H01L21/76876
摘要： A method of forming a conductive structure (e.g., bit line) of a semiconductor device includes forming a barrier metal layer on a semiconductor substrate in which structures are formed. An amorphous titanium carbon nitride layer is formed on the barrier metal layer. A tungsten seed layer is formed on the amorphous titanium carbon nitride layer under an atmosphere including a boron gas. A tungsten layer is formed on the tungsten seed layer, thus forming a bit line.
摘要翻译：形成半导体器件的导电结构（例如位线）的方法包括在形成结构的半导体衬底上形成阻挡金属层。在阻挡金属层上形成非晶氮化钛层。在包含硼气体的气氛下，在非晶态氮化钛层上形成钨种子层。在钨籽晶层上形成钨层，形成位线。

7. 发明授权

US07892919B2 Method of forming isolation layer in semiconductor device 失效
标题翻译：在半导体器件中形成隔离层的方法
公开(公告)号：US07892919B2
公开(公告)日：2011-02-22
申请号：US12163328
申请日：2008-06-27
申请人： Jung Geun Kim , Cheol Mo Jeong , Whee Won Cho
发明人： Jung Geun Kim , Cheol Mo Jeong , Whee Won Cho
IPC分类号： H01L21/8242
CPC分类号： H01L21/76232
摘要： The invention discloses a method of forming an isolation layer in a semiconductor device. The method includes providing a semiconductor substrate having a trench formed therein; forming a first insulating layer in the trench; and forming a densified second insulating layer on the first insulating layer. In the above method, a void is not generated in the isolation layer so a bending phenomenon of an active region can be reduced or prevented to improve an electrical characteristic of the semiconductor.
摘要翻译：本发明公开了一种在半导体器件中形成隔离层的方法。该方法包括提供其中形成有沟槽的半导体衬底; 在沟槽中形成第一绝缘层; 以及在所述第一绝缘层上形成致密的第二绝缘层。在上述方法中，在隔离层中不会产生空隙，因此可以减少或防止有源区的弯曲现象来改善半导体的电特性。

8. 发明申请

US20100304549A1 METHOD OF FORMING ISOLATION LAYER OF SEMICONDUCTOR DEVICE 失效
标题翻译：形成半导体器件隔离层的方法
公开(公告)号：US20100304549A1
公开(公告)日：2010-12-02
申请号：US12815317
申请日：2010-06-14
申请人： Cha Deok DONG , Whee Won Cho , Jung Geun Kim , Cheol Mo Jeong , Suk Joong Kim , Jung Gu Lee
发明人： Cha Deok DONG , Whee Won Cho , Jung Geun Kim , Cheol Mo Jeong , Suk Joong Kim , Jung Gu Lee
IPC分类号： H01L21/76
CPC分类号： H01L27/11521 , H01L21/76232
摘要： A method of forming an isolation layer of a semiconductor device includes forming first trenches in an isolation region of a semiconductor substrate. Sidewalls and a bottom surface of each of the first trenches are oxidized by a radical oxidization process to form a first oxide layer. An oxidization-prevention spacer is formed on the sidewalls of each of the first trenches. Second trenches are formed in the isolation region below the corresponding first trenches, wherein each second trench is narrower and deeper than the corresponding first trench. The second trenches are filled with a second oxide layer. The first trenches are filled with an insulating layer.
摘要翻译：形成半导体器件的隔离层的方法包括在半导体衬底的隔离区域中形成第一沟槽。每个第一沟槽的侧壁和底表面被自由基氧化过程氧化以形成第一氧化物层。在每个第一沟槽的侧壁上形成防氧化间隔物。第二沟槽形成在对应的第一沟槽下方的隔离区域中，其中每个第二沟槽比相应的第一沟槽更窄和更深。第二沟槽填充有第二氧化物层。第一沟槽填充有绝缘层。

9. 发明申请

US20080003754A1 Method of forming gate of flash memory device 失效
标题翻译：形成闪存器件门的方法
公开(公告)号：US20080003754A1
公开(公告)日：2008-01-03
申请号：US11646777
申请日：2006-12-28
申请人： Cheol Mo Jeong , Whee Won Cho , Jung Geun Kim , Seong Hwan Myung
发明人： Cheol Mo Jeong , Whee Won Cho , Jung Geun Kim , Seong Hwan Myung
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11521
摘要： A method of forming a gate of a flash memory device, including the steps of forming a gate on a semiconductor substrate and forming an oxide layer on the entire surface of the gate, forming a nitride layer on a sidewall of the oxide layer in a spacer form, performing a polishing process so that a top surface of the gate is exposed, and then stripping the nitride layer to form an opening, forming a barrier metal layer on a sidewall of the opening, and forming a tungsten layer in the opening.
摘要翻译：一种形成闪速存储器件的栅极的方法，包括以下步骤：在半导体衬底上形成栅极并在栅极的整个表面上形成氧化物层，在间隔物的氧化物层的侧壁上形成氮化物层形成，进行抛光处理使得栅极的顶表面露出，然后剥离氮化物层以形成开口，在开口的侧壁上形成阻挡金属层，并在开口中形成钨层。

10. 发明申请

US20080003745A1 Method of manufacturing a flash memory device 审中-公开
标题翻译：制造闪存装置的方法
公开(公告)号：US20080003745A1
公开(公告)日：2008-01-03
申请号：US11646860
申请日：2006-12-28
申请人： Seong Hwan Myung , Jung Geun Kim , Whee Won Cho , Cheol Mo Jeong
发明人： Seong Hwan Myung , Jung Geun Kim , Whee Won Cho , Cheol Mo Jeong
IPC分类号： H01L21/336
CPC分类号： H01L27/11524 , H01L27/115 , H01L27/11521
摘要： The present invention relates to a method of manufacturing a flash memory device. The method includes the steps of forming cell gate patterns and select transistor gate patterns on a semiconductor substrate; forming a low dielectric layer on the resultant structure; etching the low dielectric layer, leavinin gaps adjacent the cell gate patterns; and, forming a nitride layer spacer on one side wall of each of the select transistor gate patterns. The resulting flash memory device has an improved rate of change in the threshold voltage and reduces the contact resistance when a self-aligned contact method is subsequently performed.
摘要翻译：本发明涉及一种制造闪速存储器件的方法。该方法包括在半导体衬底上形成单元栅极图案和选择晶体管栅极图案的步骤; 在所得结构上形成低介电层; 蚀刻低介电层，与细胞栅极图案相邻的叶绿素间隙; 并且在每个选择晶体管栅极图案的一个侧壁上形成氮化物层间隔物。所产生的闪速存储器件在随后执行自对准接触方法时具有改善的阈值电压变化率并降低接触电阻。

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