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    • 2. 发明申请
    • CLOCK BUFFER CIRCUIT AND DATA OUTPUT CIRCUIT INCLUDING THE SAME
    • 时钟缓冲器电路和数据输出电路,包括它们
    • US20130106478A1
    • 2013-05-02
    • US13599693
    • 2012-08-30
    • Byong-mo MOONMin-su AHN
    • Byong-mo MOONMin-su AHN
    • H03L7/00
    • H03L7/0814
    • A clock buffer circuit that generates a clock signal having a random cycle and duty from an input clock signal and a data output circuit including the same. The clock buffer circuit includes a buffer unit configured to receive an input clock signal and generate an internal clock signal and a first clock signal; a delay controller configured to receive the internal clock signal from the buffer unit and generate a delayed control signal according to a first control signal and a second control signal; and a delay unit configured to generate a second clock signal according to the first clock signal received from the buffer unit and the second clock signal received from the delay controller. The delay unit is configured to generate the second clock signal by randomly delaying transmission of the first clock signal.
    • 一种时钟缓冲电路,其产生具有来自输入时钟信号的随机周期和占空比的时钟信号和包括该时钟信号的数据输出电路。 时钟缓冲电路包括缓冲单元,配置为接收输入时钟信号并产生内部时钟信号和第一时钟信号; 延迟控制器,被配置为从所述缓冲器单元接收所述内部时钟信号,并根据第一控制信号和第二控制信号产生延迟的控制信号; 以及延迟单元,被配置为根据从缓冲器单元接收的第一时钟信号和从延迟控制器接收的第二时钟信号产生第二时钟信号。 延迟单元被配置为通过随机延迟第一时钟信号的发送来产生第二时钟信号。