专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07779254B1 Mechanism to enhance and enforce multiple independent levels of security in a microprocessor memory and I/O bus controller 有权
标题翻译：在微处理器存储器和I / O总线控制器中增强和实施多个独立级别的安全性的机制
公开(公告)号：US07779254B1
公开(公告)日：2010-08-17
申请号：US11314981
申请日：2005-12-21
申请人： Julianne R. Crosmer , John G. Bendickson
发明人： Julianne R. Crosmer , John G. Bendickson
IPC分类号： H04L29/06
CPC分类号： G06F21/85 , G06F21/74
摘要： The present invention is a system and a method for extending multiple independent levels of security to a plurality of input/output buses and components connected to the buses. In an exemplary embodiment, the system may include a processing unit suitable for operation in a plurality of security level. A bus controller including security control logic may be coupled to the processing unit for restricting access and flow of information between the physical memory and the plurality of buses. The bus controller may employ base address registers to allocate and map the physical memory to control which partitions of the physical memory are accessible to each of the plurality of buses and thus, a device connected to at least one of the plurality of buses.
摘要翻译：本发明是一种用于将多个独立级别的安全性扩展到连接到总线的多个输入/输出总线和组件的系统和方法。在示例性实施例中，系统可以包括适于在多个安全级别中操作的处理单元。包括安全控制逻辑的总线控制器可以耦合到处理单元，用于限制物理存储器和多个总线之间的信息的访问和流动。总线控制器可以采用基地址寄存器来分配和映射物理存储器，以控制物理存储器的哪些分区可被多个总线中的每一个访问，并且因此连接到多个总线中的至少一个总线的设备。

2. 发明授权

US07676608B1 System for extending Multiple Independent Levels of Security (MILS) partitioning to input/output (I/O) devices 有权
标题翻译：用于将多个独立级别的安全（MILS）分区扩展到输入/输出（I / O）设备的系统
公开(公告)号：US07676608B1
公开(公告)日：2010-03-09
申请号：US11637489
申请日：2006-12-12
申请人： Julianne R. Crosmer , John G. Bendickson , Scott R. Gerhold
发明人： Julianne R. Crosmer , John G. Bendickson , Scott R. Gerhold
IPC分类号： G06F3/00
CPC分类号： G06F21/554 , G06F21/85 , G06F2221/2113
摘要： The present invention is a system for providing Multiple Independent Levels of Security (MILS) partitioning. The system includes a memory, a bus controller communicatively coupled to the memory via a memory bus, and a MILS controller communicatively coupled to the bus controller via a host-side bus, the MILS controller configured for monitoring and controlling system transactions. The system further includes a plurality of input/output (I/O) devices communicatively coupled to the MILS controller via a plurality of corresponding device-side buses. The system further includes a MILS separation kernel configured for mapping regions of the memory to a plurality of user partitions. Each I/O device included in the plurality of I/O devices is allocated to a partition included in the plurality of partitions and is isolated from MILS separation kernel space. The MILS separation kernel is configured for guaranteeing isolation of the partitions of the memory. The system further includes a processor connected to the bus controller via a processor front-side bus. The MILS controller is configured for extending MILS partitioning to the plurality of I/O devices.
摘要翻译：本发明是一种用于提供多重独立安全级别（MILS）分区的系统。该系统包括存储器，总线控制器，其通过存储器总线通信地耦合到存储器，以及MILS控制器，MILS控制器经由主机侧总线通信地耦合到总线控制器，MILS控制器被配置用于监视和控制系统事务。该系统还包括多个输入/输出（I / O）设备，其经由多个对应的设备侧总线通信地耦合到MILS控制器。该系统还包括配置用于将存储器的区域映射到多个用户分区的MILS分离内核。包括在多个I / O设备中的每个I / O设备被分配给包括在多个分区中的分区，并且与MILS分离内核空间隔离。 MILS分离内核配置为保证内存分区的隔离。该系统还包括经由处理器前端总线连接到总线控制器的处理器。 MILS控制器被配置为将MILS分区扩展到多个I / O设备。

3. 发明授权

US09701197B1 Positive acknowledgement method that information is received 有权
公开(公告)号：US09701197B1
公开(公告)日：2017-07-11
申请号：US13240396
申请日：2011-09-22
申请人： John G. Bendickson
发明人： John G. Bendickson
IPC分类号： B60K28/00 , A61B5/0484 , A61B5/0476
CPC分类号： B60K28/00 , A61B5/0476 , A61B5/04842 , A61B5/18 , A61B5/6803 , A61B2503/22 , G06F19/00 , G06F19/30
摘要： A device for acknowledging warning indicators includes an electro-encephalograph for detecting signals in the midline occipital region of the user's brain, and a display system for displaying flashing indictors having differing flashing frequencies. The electro-encephalograph detects differing signals caused by the differing flashing frequencies whenever the user observes one of the flashing indicators, and the device thereby recognizes that the user has observed the warning indicator.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式