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1. 发明授权

US08589762B2 Adaptive multi-bit error correction in endurance limited memories 失效
标题翻译：耐力有限的存储器中的自适应多位错误校正
公开(公告)号：US08589762B2
公开(公告)日：2013-11-19
申请号：US13176092
申请日：2011-07-05
申请人： Jude A. Rivers , Vijayalakshmi Srinivasan
发明人： Jude A. Rivers , Vijayalakshmi Srinivasan
IPC分类号： G11C29/00
CPC分类号： G11C29/52 , G06F11/1048 , G11C16/3418 , G11C29/028 , G11C2029/0409 , G11C2029/0411
摘要： Multi-bit stuck-at fault error recovery can be enabled by adaptive multi-bit error correction method, in which the overhead of error correction hardware is reduced without affecting the lifetime of the memory device. Error correction logic hardware is decoupled from memory blocks. An error correction logic block is partitioned such that error correction logic entries support different number of error correction capabilities based on the probability of occurrence of the different number of errors in different memory blocks. Faulty memory blocks are mapped to appropriate error correction logic entries. The mapping can be one-to-one or many-to-one depending on embodiments. The adaptive partitioning of the error correction logic entries can be configured to match projected statistical distribution of errors in logic blocks, and can reduce the total error correction logic overhead, provide sufficient error correction, and/or extend the lifetime of the memory device.
摘要翻译：可以通过自适应多位错误校正方法来实现多位卡滞故障恢复，其中降低了纠错硬件的开销，而不影响存储器件的使用寿命。纠错逻辑硬件与存储器块分离。错误校正逻辑块被分区，使得纠错逻辑条目基于在不同存储器块中出现不同数量的错误的概率来支持不同数量的纠错能力。错误的存储器块被映射到适当的纠错逻辑条目。取决于实施例，映射可以是一对一或多对一。错误校正逻辑条目的自适应分割可以被配置为匹配逻辑块中的误差的预计统计分布，并且可以减少总误差校正逻辑开销，提供足够的纠错和/或延长存储器件的寿命。

2. 发明申请

US20130013977A1 ADAPTIVE MULTI-BIT ERROR CORRECTION IN ENDURANCE LIMITED MEMORIES 失效
标题翻译：自适应多重错误修正在有限的记忆
公开(公告)号：US20130013977A1
公开(公告)日：2013-01-10
申请号：US13176092
申请日：2011-07-05
申请人： Jude A. Rivers , Vijayalakshmi Srinivasan
发明人： Jude A. Rivers , Vijayalakshmi Srinivasan
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G11C29/52 , G06F11/1048 , G11C16/3418 , G11C29/028 , G11C2029/0409 , G11C2029/0411
摘要： Multi-bit stuck-at fault error recovery can be enabled by adaptive multi-bit error correction method, in which the overhead of error correction hardware is reduced without affecting the lifetime of the memory device. Error correction logic hardware is decoupled from memory blocks. An error correction logic block is partitioned such that error correction logic entries support different number of error correction capabilities based on the probability of occurrence of the different number of errors in different memory blocks. Faulty memory blocks are mapped to appropriate error correction logic entries. The mapping can be one-to-one or many-to-one depending on embodiments. The adaptive partitioning of the error correction logic entries can be configured to match projected statistical distribution of errors in logic blocks, and can reduce the total error correction logic overhead, provide sufficient error correction, and/or extend the lifetime of the memory device.
摘要翻译：可以通过自适应多位错误校正方法来实现多位卡滞故障恢复，其中降低了纠错硬件的开销，而不影响存储器件的使用寿命。纠错逻辑硬件与存储器块分离。错误校正逻辑块被分区，使得纠错逻辑条目基于在不同存储器块中出现不同数量的错误的概率来支持不同数量的纠错能力。错误的存储器块被映射到适当的纠错逻辑条目。取决于实施例，映射可以是一对一或多对一。错误校正逻辑条目的自适应分割可以被配置为匹配逻辑块中的误差的预测统计分布，并且可以减少总误差校正逻辑开销，提供足够的纠错和/或延长存储器件的寿命。

3. 发明授权

US07958334B2 Method and apparatus for an efficient multi-path trace cache design 失效
公开(公告)号：US07958334B2
公开(公告)日：2011-06-07
申请号：US12131418
申请日：2008-06-02
申请人： Galen A. Rasche , Jude A. Rivers , Vijayalakshmi Srinivasan
发明人： Galen A. Rasche , Jude A. Rivers , Vijayalakshmi Srinivasan
IPC分类号： G06F9/00
CPC分类号： G06F12/0862 , G06F12/0897 , G06F2212/6022
摘要： A novel trace cache design and organization to efficiently store and retrieve multi-path traces. A goal is to design a trace cache, which is capable of storing multi-path traces without significant duplication in the traces. Furthermore, the effective access latency of these traces is reduced.

4. 发明授权

US07930525B2 Method and apparatus for an efficient multi-path trace cache design 失效
标题翻译：用于高效多路径跟踪缓存设计的方法和装置
公开(公告)号：US07930525B2
公开(公告)日：2011-04-19
申请号：US12110745
申请日：2008-04-28
申请人： Galen A. Rasche , Jude A. Rivers , Vijayalakshmi Srinivasan
发明人： Galen A. Rasche , Jude A. Rivers , Vijayalakshmi Srinivasan
IPC分类号： G06F9/00
CPC分类号： G06F12/0862 , G06F12/0897 , G06F2212/6022
摘要： A novel trace cache design and organization to efficiently store and retrieve multi-path traces. A goal is to design a trace cache, which is capable of storing multi-path traces without significant duplication in the traces. Furthermore, the effective access latency of these traces is reduced.
摘要翻译：一种新颖的跟踪缓存设计和组织来高效地存储和检索多路径跟踪。目标是设计跟踪缓存，其能够存储多路径跟踪，而不会在跟踪中显着重复。此外，这些迹线的有效访问延迟减少了。

5. 发明申请

US20080263326A1 METHOD AND APPARATUS FOR AN EFFICIENT MULTI-PATH TRACE CACHE DESIGN 失效
标题翻译：一种有效的多路追踪缓存设计方法与设备
公开(公告)号：US20080263326A1
公开(公告)日：2008-10-23
申请号：US12110745
申请日：2008-04-28
申请人： Galen A. Rasche , Jude A. Rivers , Vijayalakshmi Srinivasan
发明人： Galen A. Rasche , Jude A. Rivers , Vijayalakshmi Srinivasan
IPC分类号： G06F9/30 , G06F12/08
CPC分类号： G06F12/0862 , G06F12/0897 , G06F2212/6022
摘要： A novel trace cache design and organization to efficiently store and retrieve multi-path traces. A goal is to design a trace cache, which is capable of storing multi-path traces without significant duplication in the traces. Furthermore, the effective access latency of these traces is reduced.
摘要翻译：一种新颖的跟踪缓存设计和组织来高效地存储和检索多路径跟踪。目标是设计跟踪缓存，其能够存储多路径跟踪，而不会在跟踪中显着重复。此外，这些迹线的有效访问延迟减少了。

6. 发明授权

US07454573B2 Cost-conscious pre-emptive cache line displacement and relocation mechanisms 失效
标题翻译：具有成本意识的优先级缓存行位移和迁移机制
公开(公告)号：US07454573B2
公开(公告)日：2008-11-18
申请号：US11035350
申请日：2005-01-13
申请人： Alper Buyuktosunoglu , Zhigang Hu , Jude A. Rivers , John T. Robinson , Xiaowei Shen , Vijayalakshmi Srinivasan
发明人： Alper Buyuktosunoglu , Zhigang Hu , Jude A. Rivers , John T. Robinson , Xiaowei Shen , Vijayalakshmi Srinivasan
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0897 , G06F12/128 , Y02D10/13
摘要： A hardware based method for determining when to migrate cache lines to the cache bank closest to the requesting processor to avoid remote access penalty for future requests. In a preferred embodiment, decay counters are enhanced and used in determining the cost of retaining a line as opposed to replacing it while not losing the data. In one embodiment, a minimization of off-chip communication is sought; this may be particularly useful in a CMP environment.
摘要翻译：一种基于硬件的方法，用于确定何时将高速缓存行迁移到最靠近请求处理器的缓存库，以避免对未来请求的远程访问损失。在优选实施例中，衰减计数器被增强并用于确定保留线的成本，而不是在不丢失数据的情况下替换它。在一个实施例中，寻求片外通信的最小化; 这可能在CMP环境中特别有用。

7. 发明申请

US20090083492A1 COST-CONSCIOUS PRE-EMPTIVE CACHE LINE DISPLACEMENT AND RELOCATION MECHANISMS 审中-公开
标题翻译： COST-CONSCIOUS PRE-CMPE CACHE LINE位移和移动机制
公开(公告)号：US20090083492A1
公开(公告)日：2009-03-26
申请号：US12272612
申请日：2008-11-17
申请人： Alper Buyuktosunoglu , Zhigang Hu , Jude A. Rivers , John T. Robinson , Xiaowei Shen , Vijayalakshmi Srinivasan
发明人： Alper Buyuktosunoglu , Zhigang Hu , Jude A. Rivers , John T. Robinson , Xiaowei Shen , Vijayalakshmi Srinivasan
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0897 , G06F12/128 , Y02D10/13
摘要： A hardware based method for determining when to migrate cache lines to the cache bank closest to the requesting processor to avoid remote access penalty for future requests. In a preferred embodiment, decay counters are enhanced and used in determining the cost of retaining a line as opposed to replacing it while not losing the data. In one embodiment, a minimization of off-chip communication is sought; this may be particularly useful in a CMP environment.
摘要翻译：一种基于硬件的方法，用于确定何时将高速缓存行迁移到最靠近请求处理器的缓存库，以避免对未来请求的远程访问损失。在优选实施例中，衰减计数器被增强并用于确定保留线的成本，而不是在不丢失数据的情况下替换它。在一个实施例中，寻求片外通信的最小化; 这可能在CMP环境中特别有用。

8. 发明申请

US20080270702A1 METHOD AND APPARATUS FOR AN EFFICIENT MULTI-PATH TRACE CACHE DESIGN 失效
公开(公告)号：US20080270702A1
公开(公告)日：2008-10-30
申请号：US12131418
申请日：2008-06-02
申请人： Galen A. Rasche , Jude A. Rivers , Vijayalakshmi Srinivasan
发明人： Galen A. Rasche , Jude A. Rivers , Vijayalakshmi Srinivasan
IPC分类号： G06F12/00
CPC分类号： G06F12/0862 , G06F12/0897 , G06F2212/6022
摘要： A novel trace cache design and organization to efficiently store and retrieve multi-path traces. A goal is to design a trace cache, which is capable of storing multi-path traces without significant duplication in the traces. Furthermore, the effective access latency of these traces is reduced.

9. 发明授权

US07366875B2 Method and apparatus for an efficient multi-path trace cache design 失效
标题翻译：用于高效多路径跟踪缓存设计的方法和装置
公开(公告)号：US07366875B2
公开(公告)日：2008-04-29
申请号：US11069014
申请日：2005-03-01
申请人： Galen A. Rasche , Jude A. Rivers , Vijayalakshmi Srinivasan
发明人： Galen A. Rasche , Jude A. Rivers , Vijayalakshmi Srinivasan
IPC分类号： G06F9/30
CPC分类号： G06F12/0862 , G06F12/0897 , G06F2212/6022
摘要： A novel trace cache design and organization to efficiently store and retrieve multi-path traces. A goal is to design a trace cache, which is capable of storing multi-path traces without significant duplication in the traces. Furthermore, the effective access latency of these traces is reduced.
摘要翻译：一种新颖的跟踪缓存设计和组织来高效地存储和检索多路径跟踪。目标是设计跟踪缓存，其能够存储多路径跟踪，而不会在跟踪中显着重复。此外，这些迹线的有效访问延迟减少了。

10. 发明授权

US09092341B2 Methods of cache preloading on a partition or a context switch 有权
标题翻译：缓存预加载在分区或上下文切换上的方法
公开(公告)号：US09092341B2
公开(公告)日：2015-07-28
申请号：US13545304
申请日：2012-07-10
申请人： Harold W. Cain, III , Vijayalakshmi Srinivasan , Jason Zebchuk
发明人： Harold W. Cain, III , Vijayalakshmi Srinivasan , Jason Zebchuk
IPC分类号： G06F12/00 , G06F12/08 , G06F12/10 , G06F12/12
CPC分类号： G06F12/0862 , G06F12/0813 , G06F12/0866 , G06F12/1009 , G06F12/122 , G06F12/123 , G06F2212/602 , G06F2212/69
摘要： A scheme referred to as a “Region-based cache restoration prefetcher” (RECAP) is employed for cache preloading on a partition or a context switch. The RECAP exploits spatial locality to provide a bandwidth-efficient prefetcher to reduce the “cold” cache effect caused by multiprogrammed virtualization. The RECAP groups cache blocks into coarse-grain regions of memory, and predicts which regions contain useful blocks that should be prefetched the next time the current virtual machine executes. Based on these predictions, and using a simple compression technique that also exploits spatial locality, the RECAP provides a robust prefetcher that improves performance without excessive bandwidth overhead or slowdown.
摘要翻译：被称为“基于区域的高速缓存恢复预取器”（RECAP）的方案被用于在分区或上下文切换上进行高速缓存预加载。 RECAP利用空间局部性提供带宽有效的预取器，以减少由多编程虚拟化引起的“冷”缓存效应。 RECAP组将高速缓存块缓存到内存的粗粒度区域中，并预测哪些区域包含下一次执行当前虚拟机时应预取的有用块。基于这些预测，并且使用也利用空间局部性的简单压缩技术，RECAP提供了一种强大的预取器，可以在没有过多带宽开销或减速的情况下提高性能。

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