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1. 发明授权

US08059175B2 Image capture device and method of operating the same 有权
标题翻译：图像捕获装置及其操作方法
公开(公告)号：US08059175B2
公开(公告)日：2011-11-15
申请号：US11979886
申请日：2007-11-09
申请人： Ju-Seop Park , Gun-Hee Han , Seog-Heon Ham
发明人： Ju-Seop Park , Gun-Hee Han , Seog-Heon Ham
IPC分类号： H04N9/083 , H04N3/14 , H04N5/335 , H04N9/04
CPC分类号： H04N5/235 , H04N5/2355
摘要： A method for operating an image capture device having a sensor with an array of first and second pixels includes capturing an image a plurality of times with the second pixels to produce a corresponding second image signal, the second pixels being white pixels, capturing the image a single time with the first pixels to produce a corresponding first image signal, inputting selecting signals to the sensor via a row driver to obtain the first and second image signals from the first and second pixels, respectively, and converting the first and second image signals to respective digital values via an analog-to-digital converter.
摘要翻译：一种用于操作具有具有第一和第二像素的阵列的传感器的图像捕获装置的方法包括用第二像素捕获多次图像以产生对应的第二图像信号，第二像素为白色像素，捕获图像与第一像素单时间产生对应的第一图像信号，经由行驱动器将选择信号输入到传感器，以分别从第一和第二像素获得第一和第二图像信号，并将第一和第二图像信号转换为各自的数字值通过模数转换器。

2. 发明申请

US20080122961A1 Image capture device and method of operating the same 有权
标题翻译：图像捕获装置及其操作方法
公开(公告)号：US20080122961A1
公开(公告)日：2008-05-29
申请号：US11979886
申请日：2007-11-09
申请人： Ju-Seop Park , Gun-Hee Han , Seong-Heon Ham
发明人： Ju-Seop Park , Gun-Hee Han , Seong-Heon Ham
IPC分类号： H04N9/04
CPC分类号： H04N5/235 , H04N5/2355
摘要： A method for operating an image capture device having a sensor with an array of first and second pixels includes capturing an image a plurality of times with the second pixels to produce a corresponding second image signal, the second pixels being white pixels, capturing the image a single time with the first pixels to produce a corresponding first image signal, inputting selecting signals to the sensor via a row driver to obtain the first and second image signals from the first and second pixels, respectively, and converting the first and second image signals to respective digital values via an analog-to-digital converter.
摘要翻译：一种用于操作具有具有第一和第二像素的阵列的传感器的图像捕获装置的方法包括用第二像素捕获多次图像以产生对应的第二图像信号，第二像素为白色像素，捕获图像与第一像素单时间产生对应的第一图像信号，经由行驱动器将选择信号输入到传感器，以分别从第一和第二像素获得第一和第二图像信号，并将第一和第二图像信号转换为各自的数字值通过模数转换器。

3. 发明授权

US08804448B2 Method of selecting anti-fuses and method of monitoring anti-fuses 有权
标题翻译：选择防熔丝的方法和监控防熔丝的方法
公开(公告)号：US08804448B2
公开(公告)日：2014-08-12
申请号：US13461987
申请日：2012-05-02
申请人： Ju-Seop Park , Jong-Pil Son , Sin-Ho Kim , Hyoung-Joo Kim , Je-Min Ryu , Sung-Min Seo
发明人： Ju-Seop Park , Jong-Pil Son , Sin-Ho Kim , Hyoung-Joo Kim , Je-Min Ryu , Sung-Min Seo
IPC分类号： G11C7/00
CPC分类号： G11C17/16 , G11C8/10 , G11C17/18 , G11C29/027
摘要： For selecting anti-fuses in a semiconductor memory device, a decoder block may be enabled to receive selection information for selecting the anti-fuses. The selection information is decoded in the decoder block to select at least one of the anti-fuses. Target operation is performed on the selected anti-fuses. The decoder block is disabled.
摘要翻译：为了在半导体存储器件中选择抗熔丝，可以使解码器块接收用于选择抗熔丝的选择信息。选择信息在解码器块中解码以选择至少一个抗熔丝。对选定的防熔丝执行目标操作。解码器块被禁用。

4. 发明授权

US08848475B2 Fuse circuit, fuse array, semiconductor memory device and method of manufacturing semiconductor device 有权
标题翻译：保险丝电路，保险丝阵列，半导体存储器件及制造半导体器件的方法
公开(公告)号：US08848475B2
公开(公告)日：2014-09-30
申请号：US13219749
申请日：2011-08-29
申请人： Jong-Pil Son , Seong-Jin Jang , Byung-Sik Moon , Hyuck-Chai Jung , Ju-Seop Park
发明人： Jong-Pil Son , Seong-Jin Jang , Byung-Sik Moon , Hyuck-Chai Jung , Ju-Seop Park
IPC分类号： G11C17/18 , G11C17/16 , H01L27/10 , H01L23/525
CPC分类号： H01L27/101 , G11C17/16 , G11C17/18 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： A fuse circuit includes a program unit and a sensing unit. The program unit is programmed in response to a program signal and outputs a program output signal in response to a sensing enable signal. The sensing unit outputs a sensing output signal based on the program output signal and the sensing output signal indicates whether the program unit is programmed or not. The program unit includes an anti-fuse cell, a selection transistor, a program transistor and a sensing transistor. The anti-fuse cell includes at least two anti-fuse elements which are connected in parallel and are respectively broken down at different levels of a program voltage.
摘要翻译：熔丝电路包括程序单元和感测单元。程序单元响应于程序信号被编程，并且响应于感测使能信号而输出程序输出信号。感测单元基于程序输出信号输出感测输出信号，并且感测输出信号指示程序单元是否被编程。程序单元包括反熔丝单元，选择晶体管，程序晶体管和感测晶体管。反熔丝单元包括至少两个并联连接的反熔丝元件，并分别以不同的编程电压电平分解。

5. 发明申请

US20120051154A1 FUSE CIRCUIT, FUSE ARRAY, SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：保险丝电路，保险丝阵列，半导体存储器件及制造半导体器件的方法
公开(公告)号：US20120051154A1
公开(公告)日：2012-03-01
申请号：US13219749
申请日：2011-08-29
申请人： Jong-Pil SON , Seong-Jin Jang , Byung-Sik Moon , Hyuck-Chai Jung , Ju-Seop Park
发明人： Jong-Pil SON , Seong-Jin Jang , Byung-Sik Moon , Hyuck-Chai Jung , Ju-Seop Park
IPC分类号： G11C17/16 , G11C7/00 , H01L27/088 , G11C29/04 , H01L21/8236
CPC分类号： H01L27/101 , G11C17/16 , G11C17/18 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： A fuse circuit includes a program unit and a sensing unit. The program unit is programmed in response to a program signal and outputs a program output signal in response to a sensing enable signal. The sensing unit outputs a sensing output signal based on the program output signal and the sensing output signal indicates whether the program unit is programmed or not. The program unit includes an anti-fuse cell, a selection transistor, a program transistor and a sensing transistor. The anti-fuse cell includes at least two anti-fuse elements which are connected in parallel and are respectively broken down at different levels of a program voltage.
摘要翻译：熔丝电路包括程序单元和感测单元。程序单元响应于程序信号被编程，并响应于感测使能信号而输出程序输出信号。感测单元基于程序输出信号输出感测输出信号，并且感测输出信号指示程序单元是否被编程。程序单元包括反熔丝单元，选择晶体管，程序晶体管和感测晶体管。反熔丝单元包括至少两个并联连接的反熔丝元件，并分别以不同的编程电压电平分解。

6. 发明授权

US08599635B2 Fuse circuit and semiconductor memory device including the same 有权
标题翻译：保险丝电路和包括其的半导体存储器件
公开(公告)号：US08599635B2
公开(公告)日：2013-12-03
申请号：US13205966
申请日：2011-08-09
申请人： Jin-Ho Kim , Jong-Pil Son , Seong-Jin Jang , Byung-Sik Moon , Seung-Hoon Oh , Ju-Seop Park
发明人： Jin-Ho Kim , Jong-Pil Son , Seong-Jin Jang , Byung-Sik Moon , Seung-Hoon Oh , Ju-Seop Park
IPC分类号： G11C17/18
CPC分类号： G11C29/027 , G11C17/16 , G11C29/04
摘要： A fuse circuit includes a program unit, a sensing unit and a control unit. The program unit is programmed in response to a program signal, and outputs a program output signal in response to a sensing enable signal. The sensing unit includes a variable resistor unit that has a resistance that varies based on a control signal, and generates a sensing output signal based on the resistance of the variable resistor unit and the program output signal. The control unit generates the control signal having a value changed depending on operation modes, and performs a verification operation with respect to the program unit based on the sensing output signal to generate a verification result. The program unit may be re-programmed based on the verification result.
摘要翻译：熔丝电路包括程序单元，感测单元和控制单元。程序单元响应于程序信号被编程，并且响应于感测使能信号而输出程序输出信号。感测单元包括具有基于控制信号而变化的电阻的可变电阻器单元，并且基于可变电阻器单元的电阻和程序输出信号产生感测输出信号。控制单元产生具有根据操作模式改变的值的控制信号，并且基于感测输出信号执行关于节目单元的验证操作以产生验证结果。程序单元可以基于验证结果重新编程。

7. 发明授权

US08547763B2 Memory cell, methods of manufacturing memory cell, and memory device having the same 有权
标题翻译：存储单元，存储单元的制造方法以及具有该单元的存储器件
公开(公告)号：US08547763B2
公开(公告)日：2013-10-01
申请号：US13219998
申请日：2011-08-29
申请人： Jong-Pil Son , Seong-Jin Jang , Byung-Sik Moon , Doo-Young Kim , Ju-Seop Park
发明人： Jong-Pil Son , Seong-Jin Jang , Byung-Sik Moon , Doo-Young Kim , Ju-Seop Park
IPC分类号： G11C7/00 , G11C11/405
CPC分类号： G11C11/405 , G11C17/16 , G11C17/165 , H01L27/101 , H01L29/1045 , H01L29/1083 , H01L29/66537 , H01L29/7835
摘要： A memory cell includes a selection transistor on a substrate and an antifuse on the substrate. The selection transistor includes a first gate connected to a read word line, a first gate insulation layer that insulates the first gate from the substrate, a first source region connected to a bit line, and a first drain region, an impurity concentration of the first drain region being lower than an impurity concentration of the first source region. The antifuse includes a first electrode connected to a program word line and a second electrode connected to the selection transistor.
摘要翻译：存储单元包括衬底上的选择晶体管和衬底上的反熔丝。选择晶体管包括连接到读字线的第一栅极，将第一栅极与衬底绝缘的第一栅极绝缘层，连接到位线的第一源极区域和第一漏极区域，第一漏极区域的杂质浓度漏极区域低于第一源极区域的杂质浓度。反熔丝包括连接到编程字线的第一电极和连接到选择晶体管的第二电极。

8. 发明申请

US20120051164A1 MEMORY CELL, METHODS OF MANUFACTURING MEMORY CELL, AND MEMORY DEVICE HAVING THE SAME 有权
标题翻译：存储单元，制造存储单元的方法和具有该存储单元的存储器件
公开(公告)号：US20120051164A1
公开(公告)日：2012-03-01
申请号：US13219998
申请日：2011-08-29
申请人： Jong-Pil Son , Seong-Jin Jang , Byung-Sik Moon , Doo-Young Kim , Ju-Seop Park
发明人： Jong-Pil Son , Seong-Jin Jang , Byung-Sik Moon , Doo-Young Kim , Ju-Seop Park
IPC分类号： G11C29/04 , H01L21/336 , G11C7/00 , H01L27/088
CPC分类号： G11C11/405 , G11C17/16 , G11C17/165 , H01L27/101 , H01L29/1045 , H01L29/1083 , H01L29/66537 , H01L29/7835
摘要： A memory cell includes a selection transistor on a substrate and an antifuse on the substrate. The selection transistor includes a first gate connected to a read word line, a first gate insulation layer that insulates the first gate from the substrate, a first source region connected to a bit line, and a first drain region, an impurity concentration of the first drain region being lower than an impurity concentration of the first source region. The antifuse includes a first electrode connected to a program word line and a second electrode connected to the selection transistor.
摘要翻译：存储单元包括衬底上的选择晶体管和衬底上的反熔丝。选择晶体管包括连接到读字线的第一栅极，将第一栅极与衬底绝缘的第一栅极绝缘层，连接到位线的第一源极区域和第一漏极区域，第一漏极区域的杂质浓度漏极区域低于第一源极区域的杂质浓度。反熔丝包括连接到编程字线的第一电极和连接到选择晶体管的第二电极。

9. 发明申请

US20130286759A1 METHOD OF SELECTING ANTI-FUSES AND METHOD OF MONITORING ANTI-FUSES 有权
标题翻译：选择抗熔体的方法和监测抗熔融体的方法
公开(公告)号：US20130286759A1
公开(公告)日：2013-10-31
申请号：US13461987
申请日：2012-05-02
申请人： Ju-Seop Park , Jong-Pil Son , Sin-Ho Kim , Hyoung-Joo Kim , Je-Min Ryu , Sung-Min Seo
发明人： Ju-Seop Park , Jong-Pil Son , Sin-Ho Kim , Hyoung-Joo Kim , Je-Min Ryu , Sung-Min Seo
IPC分类号： G11C29/00 , G11C8/00
CPC分类号： G11C17/16 , G11C8/10 , G11C17/18 , G11C29/027
摘要： For selecting anti-fuses in a semiconductor memory device, a decoder block may be enabled to receive selection information for selecting the anti-fuses. The selection information is decoded in the decoder block to select at least one of the anti-fuses. Target operation is performed on the selected anti-fuses. The decoder block is disabled.
摘要翻译：为了在半导体存储器件中选择抗熔丝，可以使解码器块接收用于选择抗熔丝的选择信息。选择信息在解码器块中解码以选择至少一个抗熔丝。对选定的防熔丝执行目标操作。解码器块被禁用。

10. 发明授权

US08514648B2 Anti-fuse, anti-fuse circuit including the same, and method of fabricating the anti-fuse 有权
标题翻译：防熔丝，反熔丝电路包括相同，以及制造防熔丝的方法
公开(公告)号：US08514648B2
公开(公告)日：2013-08-20
申请号：US13051998
申请日：2011-03-18
申请人： Jong-Pil Son , Seong-Jin Jang , Byung-Sik Moon , Doo-Young Kim , Hyoung-Joo Kim , Ju-Seop Park
发明人： Jong-Pil Son , Seong-Jin Jang , Byung-Sik Moon , Doo-Young Kim , Hyoung-Joo Kim , Ju-Seop Park
IPC分类号： G11C17/18
CPC分类号： H01L23/5252 , G11C17/16 , G11C29/785 , H01L27/101 , H01L2924/0002 , H01L2924/00
摘要： Provided are an anti-fuse, an anti-fuse circuit, and a method of fabricating the anti-fuse. The anti-fuse includes a semiconductor substrate, an isolation region, a channel diffusion region, a gate oxide layer, and a gate electrode. The semiconductor substrate includes a top surface and a bottom portion, the bottom portion of the semiconductor substrate having a first conductivity type. The isolation region is disposed inward from the top surface of the semiconductor substrate to a first depth. The channel diffusion region is disposed inward from the top surface of the semiconductor substrate to a second depth, the second depth located at a depth where the channel diffusion region meets an upper boundary of the bottom portion of the semiconductor substrate. The channel diffusion region is surrounded by the isolation region, the first depth is a greater distance from the top surface of the semiconductor substrate than the second depth, and the channel diffusion region has a second conductivity type opposite to the first conductivity type. The gate oxide layer is disposed on the channel diffusion region, and the gate electrode is disposed on the gate oxide layer to cover a top surface of the gate oxide layer.
摘要翻译：提供反熔丝，反熔丝电路和制造反熔丝的方法。反熔丝包括半导体衬底，隔离区，沟道扩散区，栅极氧化层和栅电极。半导体衬底包括顶表面和底部，半导体衬底的底部具有第一导电类型。隔离区域从半导体衬底的顶表面向内设置到第一深度。沟道扩散区域从半导体衬底的顶表面向内设置到第二深度，第二深度位于沟道扩散区域与半导体衬底的底部的上边界相交的深度处。沟道扩散区域由隔离区域包围，第一深度比半导体衬底的顶表面的距离大于第二深度，并且沟道扩散区域具有与第一导电类型相反的第二导电类型。栅极氧化层设置在沟道扩散区上，并且栅电极设置在栅极氧化层上以覆盖栅极氧化物层的顶表面。

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