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1. 发明申请

US20180285120A1 REGISTER SPILL/FILL USING SHARED LOCAL MEMORY SPACE 审中-公开
公开(公告)号：US20180285120A1
公开(公告)日：2018-10-04
申请号：US15477030
申请日：2017-04-01
申请人： Joydeep Ray , Altug Koker , Balaji Vembu , Murali Ramadoss , Guei-Yuan Lueh , James A. Valerio , Prasoonkumar Surti , Abhishek R. Appu , Vasanth Ranganathan , Kalyan Bhairavabhatla , Arthur D. Hunter, JR. , Wei-Yu Chen , Subramaniam M. Maiyuran
发明人： Joydeep Ray , Altug Koker , Balaji Vembu , Murali Ramadoss , Guei-Yuan Lueh , James A. Valerio , Prasoonkumar Surti , Abhishek R. Appu , Vasanth Ranganathan , Kalyan Bhairavabhatla , Arthur D. Hunter, JR. , Wei-Yu Chen , Subramaniam M. Maiyuran
IPC分类号： G06F9/38 , G06F9/345 , G06F9/30 , G06F12/084 , G06T1/60 , G06T1/20 , G09G5/36
CPC分类号： G09G5/363 , G06F9/461 , G06F12/0811 , G06F12/084 , G06F12/0875 , G06F2212/1024 , G06F2212/1028 , G06F2212/455 , G09G5/001 , G09G2340/02 , G09G2350/00 , G09G2352/00 , G09G2360/08 , G09G2360/121
摘要： A mechanism is described for facilitating using of a shared local memory for register spilling/filling relating to graphics processors at computing devices. A method of embodiments, as described herein, includes reserving one or more spaces of a shared local memory (SLM) to perform one or more of spilling and filling relating to registers associated with a graphics processor of a computing device.

2. 发明申请

US20190244418A1 CONDITIONAL SHADER FOR GRAPHICS 审中-公开
公开(公告)号：US20190244418A1
公开(公告)日：2019-08-08
申请号：US16269270
申请日：2019-02-06
申请人： Prasoonkumar Surti , Karthik Vaidyanathan , Murali Ramadoss , Michael Apodaca , Abhishek Venkatesh , Devan Burke , Philip R. Laws , Subramaniam Maiyuran , Abhishek R. Appu , ElMoustapha Ould-Ahmed-Vall , Peter L. Doyle
发明人： Prasoonkumar Surti , Karthik Vaidyanathan , Murali Ramadoss , Michael Apodaca , Abhishek Venkatesh , Devan Burke , Philip R. Laws , Subramaniam Maiyuran , Abhishek R. Appu , ElMoustapha Ould-Ahmed-Vall , Peter L. Doyle
IPC分类号： G06T15/80 , G06F9/50 , G06T1/20 , G06T5/20
CPC分类号： G06T15/80 , G06F9/50 , G06F9/5011 , G06T1/20 , G06T5/20
摘要： An embodiment of a conditional shader apparatus may include a conditional pixel shader to determine if one or more pixels meet a shader condition, and a pixel regrouper communicatively coupled to the conditional pixel shader to regroup pixels based on whether the one or more pixels are determined to meet the shader condition. Another embodiment of a conditional shader apparatus may include a thread analyzer to determine if a set of threads meet a thread condition, and a conditional kernel loader communicatively coupled to the thread analyzer to load an appropriate kernel from a set of two or more kernels based on whether the set of threads are determined to meet the thread condition. Other embodiments are disclosed and claimed.

3. 发明申请

US20160189681A1 Ordering Mechanism for Offload Graphics Scheduling 有权
标题翻译：卸载图形调度的排序机制
公开(公告)号：US20160189681A1
公开(公告)日：2016-06-30
申请号：US14582972
申请日：2014-12-24
申请人： Bryan R. White , Balaji Vembu , Murali Ramadoss , Altug Koker , Aditya Navale
发明人： Bryan R. White , Balaji Vembu , Murali Ramadoss , Altug Koker , Aditya Navale
IPC分类号： G09G5/18 , G06T1/60 , G06T1/20
CPC分类号： G09G5/18 , G06T1/20 , G09G5/026 , G09G5/14 , G09G5/363 , G09G2320/106 , G09G2340/02 , G09G2360/121 , G09G2360/18 , G09G2370/16
摘要： Described herein are technologies related to a ensuring that graphics commands and graphics context are offloading and scheduled for consumption as the commands and graphics context are sent from coherent to non-coherent memory/fabric in a “processor to processor” handoff or transaction.
摘要翻译：这里描述的是与在“处理器到处理器”切换或事务中的命令和图形上下文从相干到非相干存储器/结构发送相关的确保图形命令和图形上下文被卸载并被调度用于消费的技术。

4. 发明申请

US20140267323A1 MEMORY MAPPING FOR A GRAPHICS PROCESSING UNIT 有权
标题翻译：图形处理单元的存储映射
公开(公告)号：US20140267323A1
公开(公告)日：2014-09-18
申请号：US13851400
申请日：2013-03-27
申请人： Altug Koker , Balaji Vembu , Murali Ramadoss , Aditya Navale
发明人： Altug Koker , Balaji Vembu , Murali Ramadoss , Aditya Navale
IPC分类号： G06T1/60
CPC分类号： G06T1/60 , G06F9/485 , G06F12/1009 , G06F12/128 , G06T1/20
摘要： An electronic device is described herein. The electronic device may include a page walker module to receive a page request of a graphics processing unit (GPU). The page walker module may detect a page fault associated with the page request. The electronic device may include a controller, at least partially comprising hardware logic. The controller is to monitor execution of the page request having the page fault. The controller determines whether to suspend execution of a work item at the GPU associated with the page request having the page fault, or to continue execution of the work item based on factors associated with the page request.
摘要翻译：本文描述了一种电子设备。电子设备可以包括页面助行器模块，用于接收图形处理单元（GPU）的页面请求。页面助行器模块可以检测与页面请求相关联的页面错误。电子设备可以包括至少部分地包括硬件逻辑的控制器。控制器将监视具有页面错误的页面请求的执行。控制器确定是否在与具有页面错误的页面请求相关联的GPU处挂起工作项的执行，或者基于与页面请求相关联的因素来继续执行工作项。

5. 发明申请

US20140068626A1 Direct Ring 3 Submission of Processing Jobs to Adjunct Processors 有权
标题翻译：直接环3提交处理作业到辅助处理器
公开(公告)号：US20140068626A1
公开(公告)日：2014-03-06
申请号：US13993089
申请日：2011-12-30
申请人： Altug Koker , Aditya Navale , Balaji Vembu , Murali Ramadoss
发明人： Altug Koker , Aditya Navale , Balaji Vembu , Murali Ramadoss
IPC分类号： G06F9/50
CPC分类号： G06F9/50 , G06F9/4812 , G06F9/545 , G06F12/1491 , G06F15/167
摘要： Transitions to ring 0, each time an application wants to use an adjunct processor, are avoided, saving central processor operating cycles and improving efficiency. Instead, initially each application is registered and setup to use adjunct processor resources in ring 3.
摘要翻译：每次应用程序想要使用辅助处理器时，转换到0，避免中断处理器运行周期并提高效率。相反，最初每个应用程序都被注册并设置为在环3中使用辅助处理器资源。

6. 发明授权

US09678795B2 Direct ring 3 submission of processing jobs to adjunct processors 有权
公开(公告)号：US09678795B2
公开(公告)日：2017-06-13
申请号：US13993089
申请日：2011-12-30
申请人： Altug Koker , Aditya Navale , Balaji Vembu , Murali Ramadoss
发明人： Altug Koker , Aditya Navale , Balaji Vembu , Murali Ramadoss
IPC分类号： G06F9/46 , G06F9/50 , G06F9/48 , G06F15/167 , G06F9/54 , G06F12/14
CPC分类号： G06F9/50 , G06F9/4812 , G06F9/545 , G06F12/1491 , G06F15/167
摘要： Transitions to ring 0, each time an application wants to use an adjunct processor, are avoided, saving central processor operating cycles and improving efficiency. Instead, initially each application is registered and setup to use adjunct processor resources in ring 3.

7. 发明申请

US20130159820A1 DYNAMIC ERROR HANDLING USING PARITY AND REDUNDANT ROWS 有权
标题翻译：使用奇偶性和冗余行动态动态错误处理
公开(公告)号：US20130159820A1
公开(公告)日：2013-06-20
申请号：US13327845
申请日：2011-12-16
申请人： Altug Koker , Shailesh Shah , Aditya Navale , Murali Ramadoss , Satish K. Damaraju
发明人： Altug Koker , Shailesh Shah , Aditya Navale , Murali Ramadoss , Satish K. Damaraju
IPC分类号： H03M13/09 , G06F11/10
CPC分类号： G06F11/1048 , G06F11/10 , G06F11/1008 , G06F11/1076 , H03M13/09 , H03M13/11 , H04L1/0057
摘要： Embodiments of an invention for dynamic error correction using parity and redundant rows are disclosed. In one embodiment, an apparatus includes a storage structure, parity logic, an error storage space, and an error event generator. The storage structure is to store a plurality of data values. The parity logic is to detect a parity error in a data value stored in the storage structure. The error storage space is to store an indication of a detection of the parity error. The error event generator is to generate an event in response to the indication of the parity error being stored in the error storage space.
摘要翻译：公开了使用奇偶校验和冗余行的动态纠错的发明的实施例。在一个实施例中，装置包括存储结构，奇偶校验逻辑，错误存储空间和错误事件发生器。存储结构是存储多个数据值。奇偶校验逻辑是检测存储在存储结构中的数据值中的奇偶校验错误。错误存储空间是存储奇偶校验错误检测的指示。错误事件发生器响应于存储在错误存储空间中的奇偶校验错误的指示而生成事件。

8. 发明授权

US09075741B2 Dynamic error handling using parity and redundant rows 有权
标题翻译：使用奇偶校验和冗余行的动态错误处理
公开(公告)号：US09075741B2
公开(公告)日：2015-07-07
申请号：US13327845
申请日：2011-12-16
申请人： Altug Koker , Shailesh Shah , Aditya Navale , Murali Ramadoss , Satish K. Damaraju
发明人： Altug Koker , Shailesh Shah , Aditya Navale , Murali Ramadoss , Satish K. Damaraju
IPC分类号： G06F11/00 , G06F11/10 , H03M13/09 , H04L1/00 , H03M13/11
CPC分类号： G06F11/1048 , G06F11/10 , G06F11/1008 , G06F11/1076 , H03M13/09 , H03M13/11 , H04L1/0057
摘要： Embodiments of an invention for dynamic error correction using parity and redundant rows are disclosed. In one embodiment, an apparatus includes a storage structure, parity logic, an error storage space, and an error event generator. The storage structure is to store a plurality of data values. The parity logic is to detect a parity error in a data value stored in the storage structure. The error storage space is to store an indication of a detection of the parity error. The error event generator is to generate an event in response to the indication of the parity error being stored in the error storage space.
摘要翻译：公开了使用奇偶校验和冗余行的动态纠错的发明的实施例。在一个实施例中，装置包括存储结构，奇偶校验逻辑，错误存储空间和错误事件发生器。存储结构是存储多个数据值。奇偶校验逻辑是检测存储在存储结构中的数据值中的奇偶校验错误。错误存储空间是存储奇偶校验错误检测的指示。错误事件发生器响应于存储在错误存储空间中的奇偶校验错误的指示而生成事件。

9. 发明申请

US20190324919A1 Page Tables for Granular Allocation of Memory Pages 审中-公开
公开(公告)号：US20190324919A1
公开(公告)日：2019-10-24
申请号：US16457019
申请日：2019-06-28
申请人： Altug Koker , Ankur Shah , Murali Ramadoss , Niranjan Cooray
发明人： Altug Koker , Ankur Shah , Murali Ramadoss , Niranjan Cooray
IPC分类号： G06F12/1009 , G06F12/1027
摘要： Systems and methods related to memory paging and memory translation are disclosed. The systems may allow allocation of memory pages with increased diversity in the memory page sizes using page tables dimensioned in a manner that optimizes memory usage by the data structures of the page system.

10. 发明授权

US09317892B2 Method and device to augment volatile memory in a graphics subsystem with non-volatile memory 有权
标题翻译：在具有非易失性存储器的图形子系统中增加易失性存储器的方法和装置
公开(公告)号：US09317892B2
公开(公告)日：2016-04-19
申请号：US13977261
申请日：2011-12-28
申请人： Bryan E. Veal , Travis T. Schluessler , Murali Ramadoss , Balaji Vembu
发明人： Bryan E. Veal , Travis T. Schluessler , Murali Ramadoss , Balaji Vembu
IPC分类号： G09G5/39 , G06T1/60 , G11C16/34
CPC分类号： G06T1/60 , G11C16/349
摘要： Methods and devices to augment volatile memory in a graphics subsystem with certain types of non-volatile memory are described. In one embodiment, includes storing one or more static or near-static graphics resources in a non-volatile random access memory (NVRAM). The NVRAM is directly accessible by a graphics processor using at least memory store and load commands. The method also includes a graphics processor executing a graphics application. The graphics processor sends a request using a memory load command for an address corresponding to at least one static or near-static graphics resources stored in the NVRAM. The method also includes directly loading the requested graphics resource from the NVRAM into a cache for the graphics processor in response to the memory load command.
摘要翻译：描述了在具有某些类型的非易失性存储器的图形子系统中增加易失性存储器的方法和装置。在一个实施例中，包括将一个或多个静态或近静态图形资源存储在非易失性随机存取存储器（NVRAM）中。 NVRAM可直接由图形处理器使用，至少使用内存存储和加载命令。该方法还包括执行图形应用的图形处理器。图形处理器使用存储器加载命令来发送对应于存储在NVRAM中的至少一个静态或近静态图形资源的地址的请求。该方法还包括响应于存储器加载命令将所请求的图形资源从NVRAM直接加载到图形处理器的高速缓存中。

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