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1. 发明申请

US20100219481A1 METHOD FOR MANUFACTURING A DUAL WORK FUNCTION SEMICONDUCTOR DEVICE AND THE SEMICONDUCTOR DEVICE MADE THEREOF 审中-公开
标题翻译：制造双功能半导体器件的半导体器件及其半导体器件的制造方法
公开(公告)号：US20100219481A1
公开(公告)日：2010-09-02
申请号：US12684803
申请日：2010-01-08
申请人： Joshua Tseng , Yasutoshi Okuno , Lars-Ake Ragnarsson , Tom Schram , Stefan Kubicek , Thomas Y. Hoffmann , Naohisa Sengoku
发明人： Joshua Tseng , Yasutoshi Okuno , Lars-Ake Ragnarsson , Tom Schram , Stefan Kubicek , Thomas Y. Hoffmann , Naohisa Sengoku
IPC分类号： H01L27/092 , H01L21/28
摘要： A method for manufacturing a dual work function device is disclosed. In one aspect, the process includes a first and second region in a substrate. The method includes forming a first transistor in the first region which has a first work function. Subsequently, a second transistor is formed in the second region having a different work function. The process of forming the first transistor includes providing a first gate dielectric stack having a first gate dielectric layer and a first gate dielectric capping layer on the first gate dielectric layer, performing a thermal treatment to modify the first gate dielectric stack, the modified first gate dielectric stack defining the first work function, providing a first metal gate electrode layer on the modified first gate dielectric stack, and patterning the first metal gate electrode layer and the modified first gate dielectric stack.
摘要翻译：公开了一种用于制造双功能功能装置的方法。在一个方面，该方法包括在基底中的第一和第二区域。该方法包括在具有第一功能的第一区域中形成第一晶体管。随后，在具有不同功函数的第二区域中形成第二晶体管。形成第一晶体管的过程包括提供在第一栅极介电层上具有第一栅极介电层和第一栅极介电覆盖层的第一栅极电介质堆叠，执行热处理以修改第一栅极电介质堆叠，修改的第一栅极限定第一功函数的电介质叠层，在修改的第一栅极电介质堆叠上提供第一金属栅极电极层，以及对第一金属栅极电极层和修改的第一栅极电介质堆叠进行构图。

2. 发明授权

US08211812B2 Method for fabricating a high-K dielectric layer 失效
标题翻译：高K电介质层的制造方法
公开(公告)号：US08211812B2
公开(公告)日：2012-07-03
申请号：US12104353
申请日：2008-04-16
申请人： Lars-Ake Ragnarsson , Paul Zimmerman , Kazuhiko Yamamoto , Tom Schram , Wim Deweerd , David Brunco , Stefan De Gendt , Wilfried Vandervorst
发明人： Lars-Ake Ragnarsson , Paul Zimmerman , Kazuhiko Yamamoto , Tom Schram , Wim Deweerd , David Brunco , Stefan De Gendt , Wilfried Vandervorst
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/316 , C23C16/56 , H01L21/28185 , H01L21/28194 , H01L21/31116 , H01L21/31122 , H01L21/31604 , H01L21/31637 , H01L21/31641 , H01L21/31645 , H01L29/517 , H01L2924/0002 , H01L2924/00
摘要： One inventive aspect relates to a method for fabricating a high-k dielectric layer. The method comprises depositing onto a substrate a layer of a high-k dielectric material having a first thickness. The high-k dielectric material has a bulk density value and the first thickness is so that the high-k dielectric layer has a density of at least the bulk density value of the high-k dielectric material minus about 10%. The method further comprises thinning the high-k dielectric layer to a second thickness. Another inventive aspect relates to a semiconductor device comprising a high-k dielectric layer as fabricated by the method.
摘要翻译：本发明的一个方面涉及一种用于制造高k电介质层的方法。该方法包括在基底上沉积具有第一厚度的高k电介质材料的层。高k电介质材料具有体积密度值，第一厚度使得高k电介质层具有至少高k电介质材料的体积密度值减去约10％的密度。该方法还包括将高k电介质层变薄至第二厚度。另一个发明方面涉及包括通过该方法制造的高k电介质层的半导体器件。

3. 发明申请

US20080308881A1 Method for Controlled Formation of a Gate Dielectric Stack 审中-公开
标题翻译：控制形成栅介质堆叠的方法
公开(公告)号：US20080308881A1
公开(公告)日：2008-12-18
申请号：US11972615
申请日：2008-01-10
申请人： Stefan De Gendt , Lars-Ake Ragnarsson , Sven Van Elshocht , Shih-Hsun Chang , Christoph Adelmann , Tom Schram
发明人： Stefan De Gendt , Lars-Ake Ragnarsson , Sven Van Elshocht , Shih-Hsun Chang , Christoph Adelmann , Tom Schram
IPC分类号： H01L21/28 , H01L29/78 , H01L29/92 , H01L21/02
CPC分类号： H01L21/28176 , H01L21/28264 , H01L29/20 , H01L29/517
摘要： The present disclosure relates to methods for forming a gate stack in a MOSFET device and to MOSFET devices obtainable through such methods. In exemplary methods described herein, a rare-earth-containing layer is deposited on a layer of a silicon-containing dielectric material. Before these layers are annealed, a gate electrode material is deposited on the rare-earth-containing layer. Annealing is performed after the deposition of the gate electrode material, such that a rare earth silicate layer is formed.
摘要翻译：本公开涉及在MOSFET器件中形成栅极堆叠的方法以及通过这些方法可获得的MOSFET器件。在本文所述的示例性方法中，含稀土层被沉积在含硅介电材料的层上。在这些层退火之前，在稀土层上沉积栅电极材料。在沉积栅电极材料之后进行退火，从而形成稀土硅酸盐层。

4. 发明申请

US20080265380A1 METHOD FOR FABRICATING A HIGH-K DIELECTRIC LAYER 失效
标题翻译：制造高K电介质层的方法
公开(公告)号：US20080265380A1
公开(公告)日：2008-10-30
申请号：US12104353
申请日：2008-04-16
申请人： Lars-Ake Ragnarsson , Paul Zimmerman , Kazuhiko Yamamoto , Tom Schram , Wim Deweerd , David Brunco , Stefan De Gendt , Wilfried Vandervorst
发明人： Lars-Ake Ragnarsson , Paul Zimmerman , Kazuhiko Yamamoto , Tom Schram , Wim Deweerd , David Brunco , Stefan De Gendt , Wilfried Vandervorst
IPC分类号： H01L23/58 , H01L21/469
CPC分类号： H01L21/316 , C23C16/56 , H01L21/28185 , H01L21/28194 , H01L21/31116 , H01L21/31122 , H01L21/31604 , H01L21/31637 , H01L21/31641 , H01L21/31645 , H01L29/517 , H01L2924/0002 , H01L2924/00
摘要： One inventive aspect relates to a method for fabricating a high-k dielectric layer. The method comprises depositing onto a substrate a layer of a high-k dielectric material having a first thickness. The high-k dielectric material has a bulk density value and the first thickness is so that the high-k dielectric layer has a density of at least the bulk density value of the high-k dielectric material minus about 10%. The method further comprises thinning the high-k dielectric layer to a second thickness. Another inventive aspect relates to a semiconductor device comprising a high-k dielectric layer as fabricated by the method.
摘要翻译：本发明的一个方面涉及一种用于制造高k电介质层的方法。该方法包括在基底上沉积具有第一厚度的高k电介质材料的层。高k电介质材料具有体积密度值，第一厚度使得高k电介质层具有至少高k电介质材料的体积密度值减去约10％的密度。该方法还包括将高k电介质层变薄至第二厚度。另一个发明方面涉及包括通过该方法制造的高k电介质层的半导体器件。

5. 发明授权

US08021948B2 Scalable interpoly dielectric stacks with improved immunity to program saturation 有权
标题翻译：可扩展的互补电介质堆叠，具有提高的编程饱和度的免疫力
公开(公告)号：US08021948B2
公开(公告)日：2011-09-20
申请号：US12338015
申请日：2008-12-18
申请人： Bogdan Govoreanu , Stefan De Gendt , Sven Van Elshocht , Tom Schram
发明人： Bogdan Govoreanu , Stefan De Gendt , Sven Van Elshocht , Tom Schram
IPC分类号： H01L29/72
CPC分类号： H01L29/7881 , H01L29/513 , H01L29/66825
摘要： A method for manufacturing a non-volatile memory device is described. The method comprises growing a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored. A non-volatile memory device is also described. In the non-volatile memory device, the interpoly/blocking dielectric comprises a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored, the siliconoxide consuming material having consumed at least part of the upper layer.
摘要翻译：描述了用于制造非易失性存储器件的方法。该方法包括在氧化硅消耗材料中生长一层，例如。 DyScO，在存储电荷的层的上层之上。还描述了非易失性存储器件。在非易失性存储器件中，多晶硅/绝缘电介质包括一层二氧化硅消耗材料， DyScO，在存储电荷的层的上层的顶部，消耗了上层的至少一部分的氧化硅消耗材料。

6. 发明授权

US08441064B2 Scalable interpoly dielectric stacks with improved immunity to program saturation 有权
标题翻译：可扩展的互补电介质堆叠，具有提高的编程饱和度的免疫力
公开(公告)号：US08441064B2
公开(公告)日：2013-05-14
申请号：US13207961
申请日：2011-08-11
申请人： Bogdan Govoreanu , Stefan De Gendt , Sven Van Elshocht , Tom Schram
发明人： Bogdan Govoreanu , Stefan De Gendt , Sven Van Elshocht , Tom Schram
IPC分类号： H01L29/72
CPC分类号： H01L29/7881 , H01L29/513 , H01L29/66825
摘要： A method for manufacturing a non-volatile memory device is described. The method comprises growing a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored. A non-volatile memory device is also described. In the non-volatile memory device, the interpoly/blocking dielectric comprises a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored, the siliconoxide consuming material having consumed at least part of the upper layer.
摘要翻译：描述了用于制造非易失性存储器件的方法。该方法包括在氧化硅消耗材料中生长一层，例如。 DyScO，在存储电荷的层的上层之上。还描述了非易失性存储器件。在非易失性存储器件中，多晶硅/绝缘电介质包括一层二氧化硅消耗材料， DyScO，在存储电荷的层的上层的顶部，消耗了上层的至少一部分的氧化硅消耗材料。

7. 发明申请

US20080164581A1 ELECTRONIC DEVICE AND PROCESS FOR MANUFACTURING THE SAME 审中-公开
标题翻译：电子设备及其制造方法
公开(公告)号：US20080164581A1
公开(公告)日：2008-07-10
申请号：US11969679
申请日：2008-01-04
申请人： Hag-Ju Cho , Tom Schram , Stefan De Gendt
发明人： Hag-Ju Cho , Tom Schram , Stefan De Gendt
IPC分类号： H01L21/283 , H01L23/58
CPC分类号： H01L29/513 , H01L21/28088 , H01L21/28194 , H01L29/4966 , H01L29/517 , H01L29/518 , H01L2924/0002 , H01L2924/00
摘要： An electronic device and a process for manufacturing the same are disclosed. In one aspect, the device comprises an electrode comprising a metal compound selected from the group of tantalum carbide, tantalum carbonitride, hafnium carbide and hafnium carbonitride. The device further comprises a high-k dielectric layer of a hafnium oxide comprising nitrogen and silicon, the high-k dielectric layer having a k value of at least 4.0. The device further comprises a nitrogen and/or silicon and/or carbon barrier layer placed between the electrode and the high-k dielectric layer. The nitrogen and/or silicon and/or carbon barrier layer comprises one or more metal oxides, the metal of the metal oxides being selected from the group of lanthanides, aluminium or hafnium.
摘要翻译：公开了一种电子设备及其制造方法。一方面，该装置包括一种包含选自碳化钽，碳氮化钽，碳化铪和碳氮化铪的金属化合物的电极。该器件还包括包含氮和硅的氧化铪的高k电介质层，所述高k电介质层的k值至少为4.0。该装置还包括置于电极和高k电介质层之间的氮和/或硅和/或碳阻挡层。氮和/或硅和/或碳阻挡层包含一种或多种金属氧化物，金属氧化物的金属选自镧系元素，铝或铪。

8. 发明申请

US20070215951A1 SEMICONDUCTOR DEVICES HAVING SILICIDED ELECTRODES 审中-公开
标题翻译：具有硅电极的半导体器件
公开(公告)号：US20070215951A1
公开(公告)日：2007-09-20
申请号：US11750916
申请日：2007-05-18
申请人： Tom Schram , Jacob Hooker , Marcus Henricus van Dal
发明人： Tom Schram , Jacob Hooker , Marcus Henricus van Dal
IPC分类号： H01L29/94
CPC分类号： H01L21/28097 , H01L21/823418 , H01L21/823443 , H01L21/823814 , H01L21/823835 , H01L29/4975 , H01L29/6659 , H01L29/7833
摘要： The invention relates to a method for fabricating a semiconductor device having a semiconductor body that comprises a first semiconductor structure having a dielectric layer and a first conductor, and a second semiconductor structure having a dielectric layer and a second conductor, that part of the first conductor which adjoins the dielectric layer having a work function different from the work function of the corresponding part of the second conductor. In one embodiment of the invention, after the dielectric layer has been applied to the semiconductor body, a metal layer is applied to the said dielectric layer, and then a silicon layer is deposited on the metal layer and is brought into reaction with the metal layer at the location of the first semiconductor structure, forming a metal silicide. In one embodiment, those parts of the conductors which have different work functions are formed by etching a layer other than the silicon layer, in particular a metal layer, at the location of one of the two semiconductor structures. Furthermore, a further metal layer is applied over the silicon layer and is used to form a further metal silicide at the location of the second transistor. One embodiment of the invention is particularly suitable for use in CMOS technology and results in both PMOS and NMOS transistors with favourable properties.
摘要翻译：本发明涉及一种半导体器件的制造方法，该半导体器件具有包括具有电介质层和第一导体的第一半导体结构的半导体本体，以及具有电介质层和第二导体的第二半导体结构，该第一导体其与介电层邻接，其功函数不同于第二导体的相应部分的功函数。在本发明的一个实施例中，在将介电层施加到半导体本体之后，将金属层施加到所述介电层上，然后在该金属层上沉积硅层并与金属层反应在第一半导体结构的位置处形成金属硅化物。在一个实施例中，通过在两个半导体结构之一的位置处蚀刻除了硅层以外的层，特别是金属层，形成具有不同功函数的导体的这些部分。此外，在硅层上施加另外的金属层，并且用于在第二晶体管的位置形成另外的金属硅化物。本发明的一个实施例特别适用于CMOS技术，并且导致具有良好特性的PMOS和NMOS晶体管。

9. 发明申请

US20090166715A1 Scalable Interpoly Dielectric Stacks With Improved Immunity To Program Saturation 有权
标题翻译：可扩展的Interpoly电介质堆叠，具有提高程序饱和度的抗扰度
公开(公告)号：US20090166715A1
公开(公告)日：2009-07-02
申请号：US12338015
申请日：2008-12-18
申请人： Bogdan Govoreanu , Stefan De Gendt , Sven Van Elshocht , Tom Schram
发明人： Bogdan Govoreanu , Stefan De Gendt , Sven Van Elshocht , Tom Schram
IPC分类号： H01L29/792 , H01L21/28
CPC分类号： H01L29/7881 , H01L29/513 , H01L29/66825
摘要： A method for manufacturing a non-volatile memory device is described. The method comprises growing a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored. A non-volatile memory device is also described. In the non-volatile memory device, the interpoly/blocking dielectric comprises a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored, the siliconoxide consuming material having consumed at least part of the upper layer.
摘要翻译：描述了用于制造非易失性存储器件的方法。该方法包括在氧化硅消耗材料中生长一层，例如。 DyScO，在存储电荷的层的上层之上。还描述了非易失性存储器件。在非易失性存储器件中，多晶硅/绝缘电介质包括一层二氧化硅消耗材料， DyScO，在存储电荷的层的上层的顶部，消耗了上层的至少一部分的氧化硅消耗材料。

10. 发明授权

US07226827B2 Method for fabricating semiconductor devices having silicided electrodes 有权
标题翻译：制造具有硅化物电极的半导体器件的方法
公开(公告)号：US07226827B2
公开(公告)日：2007-06-05
申请号：US10978786
申请日：2004-10-18
申请人： Tom Schram , Jacob Christopher Hooker , Marcus Johannes Henricus van Dal
发明人： Tom Schram , Jacob Christopher Hooker , Marcus Johannes Henricus van Dal
IPC分类号： H01L21/8238 , H01L21/44
CPC分类号： H01L21/28097 , H01L21/823418 , H01L21/823443 , H01L21/823814 , H01L21/823835 , H01L29/4975 , H01L29/6659 , H01L29/7833
摘要： The invention relates to a method for fabricating a semiconductor device having a semiconductor body that comprises a first semiconductor structure having a dielectric layer and a first conductor, and a second semiconductor structure having a dielectric layer and a second conductor, that part of the first conductor which adjoins the dielectric layer having a work function different from the work function of the corresponding part of the second conductor. In one embodiment of the invention, after the dielectric layer has been applied to the semiconductor body, a metal layer is applied to the said dielectric layer, and then a silicon layer is deposited on the metal layer and is brought into reaction with the metal layer at the location of the first semiconductor structure, forming a metal silicide. In one embodiment, those parts of the conductors which have different work functions are formed by etching a layer other than the silicon layer, in particular a metal layer, at the location of one of the two semiconductor structures. Furthermore, a further metal layer is applied over the silicon layer and is used to form a further metal silicide at the location of the second transistor. One embodiment of the invention is particularly suitable for use in CMOS technology and results in both PMOS and NMOS transistors with favorable properties.
摘要翻译：本发明涉及一种半导体器件的制造方法，该半导体器件具有包括具有电介质层和第一导体的第一半导体结构的半导体本体，以及具有电介质层和第二导体的第二半导体结构，该第一导体其与介电层邻接，其功函数不同于第二导体的相应部分的功函数。在本发明的一个实施例中，在将介电层施加到半导体本体之后，将金属层施加到所述介电层上，然后在该金属层上沉积硅层并与金属层反应在第一半导体结构的位置处形成金属硅化物。在一个实施例中，通过在两个半导体结构之一的位置处蚀刻除了硅层以外的层，特别是金属层，形成具有不同功函数的导体的这些部分。此外，在硅层上施加另外的金属层，并且用于在第二晶体管的位置形成另外的金属硅化物。本发明的一个实施例特别适用于CMOS技术，并且导致具有良好特性的PMOS和NMOS晶体管。

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