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1. 发明授权

US06721885B1 Reducing start-up time and avoiding customer-induced system failures for personal computers 失效
标题翻译：减少启动时间，避免客户导致的个人电脑系统故障
公开(公告)号：US06721885B1
公开(公告)日：2004-04-13
申请号：US09658130
申请日：2000-09-08
申请人： Joseph Wayne Freeman , Joseph Franklin Garvey , Steven D. Goodman , William Fred Keown, Jr. , Randall S. Springfield
发明人： Joseph Wayne Freeman , Joseph Franklin Garvey , Steven D. Goodman , William Fred Keown, Jr. , Randall S. Springfield
IPC分类号： G06F15177
CPC分类号： G06F9/4401 , G06F11/2289
摘要： Disclosed is a method for reducing power-up time and avoiding customer-induced failures of computer systems during power-up. An intrusion switch, which is connected to the inside frame of the computer system is utilized. The intrusion switch signals the BIOS of the computer system whenever the cover of the computer's system unit is opened. The BIOS controls the POST operation during power-up of the computer system. During an initial power-up of the computer system, the POST configuration code examines and configures the hardware and sets the applicable registers, etc. At the end of the POST configuration code, the register values are stored in non-volatile storage. During a subsequent power-up of the computer system, a check is made to see if the cover of the system had been opened. When the cover has not been opened, the BIOS assumes that no changed has occurred in the hardware configuration and the BIOS restores the register values from non-volatile storage without completing the POST operation. When the cover has been opened, the BIOS discards the register values and initiates the POST operation, i.e., a full configuration operation is performed and new values stored in the registers and non-volatile storage element.
摘要翻译：公开了一种在上电期间减少上电时间并避免客户导致的计算机系统故障的方法。使用连接到计算机系统的内部框架的入侵开关。每当打开计算机系统单元的盖子时，入侵开关就会通知计算机系统的BIOS。 BIOS在电脑系统启动期间控制POST操作。在计算机系统的初始上电期间，POST配置代码检查和配置硬件并设置适用的寄存器等。在POST配置代码结束时，寄存器值存储在非易失性存储器中。在计算机系统的随后上电期间，检查系统的盖是否已打开。当盖子尚未打开时，BIOS假定在硬件配置中没有发生任何变化，BIOS会从非易失性存储器中恢复寄存器值，而无需完成POST操作。当盖子打开时，BIOS将丢弃寄存器值并启动POST操作，即执行完整配置操作，并将新值存储在寄存器和非易失性存储元件中。

2. 发明授权

US07519793B2 Facilitating inter-DSP data communications 失效
标题翻译：促进DSP间数据通信
公开(公告)号：US07519793B2
公开(公告)日：2009-04-14
申请号：US11944028
申请日：2007-11-21
申请人： Youseff Abdelilah , Bartholomew Blaner , Gordon Taylor Davis , Jeffrey Haskell Derby , Joseph Franklin Garvey , Malcolm Scott Ware , Hua Ye
发明人： Youseff Abdelilah , Bartholomew Blaner , Gordon Taylor Davis , Jeffrey Haskell Derby , Joseph Franklin Garvey , Malcolm Scott Ware , Hua Ye
IPC分类号： G06F13/16 , G06F15/163
CPC分类号： G06F13/28
摘要： A method, computer program product and system for facilitating inter-digital signal processing (DSP) data communications. A direct memory access (DMA) controller may be configured to facilitate transfers of data between a first and a second DSP processor core coupled to the DMA controller. The DMA controller may read a data structure, referred to as a “buffer descriptor block,” to perform the data transfer. The buffer descriptor block may store both a source address and a destination address indicating where the data is to be retrieved and stored. The buffer descriptor block may further store a value, e.g., number of bytes, indicating a size of the data to be transferred. The DMA controller may then transfer the data located at the source address in the first DSP processor core, with a size, e.g., number of bytes, indicated from the buffer descriptor block, to the destination address in the second DSP processor core.
摘要翻译：一种用于促进数字间数字信号处理（DSP）数据通信的方法，计算机程序产品和系统。直接存储器访问（DMA）控制器可以被配置为便于在耦合到DMA控制器的第一和第二DSP处理器核之间传输数据。 DMA控制器可以读取被称为“缓冲器描述符块”的数据结构来执行数据传送。缓冲器描述符块可以存储指示要检索和存储数据的源地址和目的地址。缓冲器描述符块还可以存储指示要传送的数据的大小的值，例如字节数。然后，DMA控制器可以将位于第一DSP处理器核心中的源地址处的数据以从缓冲器描述符块指示的大小（例如，字节数）传送到第二DSP处理器核心中的目的地地址。

3. 发明授权

US07036117B2 Optimal code generation for structured assembly language expressions 失效
标题翻译：结构化汇编语言表达式的最优代码生成
公开(公告)号：US07036117B2
公开(公告)日：2006-04-25
申请号：US09939378
申请日：2001-08-24
申请人： Joseph Franklin Garvey
发明人： Joseph Franklin Garvey
IPC分类号： G06F9/45
CPC分类号： G06F8/427 , G06F8/443
摘要： An optimal code generator for generating structured assembly language expressions is disclosed. Because of the equivalence between unit structured assembly language expressions and the code implementing them, it is possible to represent complex structured assembly language expressions as a vector of unit structured assembly language expressions. A set of rules for systematic manipulation is utilized to allow logical operations on the vector representation of structured assembly language expressions to result in optimal code. Using the equivalence between the code and unit structured assembly language expressions allows the vector representation of a structured assembly language expression to be translated directly into code.
摘要翻译：公开了一种用于生成结构化汇编语言表达式的最优代码生成器。由于单元结构化汇编语言表达式和实现它们的代码之间的等价性，可以将复杂的结构化汇编语言表达式表示为单位结构化汇编语言表达式的向量。利用一组系统操纵的规则来允许对结构化汇编语言表达式的向量表示进行逻辑运算，从而获得最佳代码。使用代码和单元结构化汇编语言表达式之间的等价性，允许将结构化汇编语言表达式的向量表示直接转换为代码。

4. 发明授权

US07325122B2 Facilitating inter-DSP data communications 失效
标题翻译：促进DSP间数据通信
公开(公告)号：US07325122B2
公开(公告)日：2008-01-29
申请号：US10783757
申请日：2004-02-20
申请人： Youseff Abdelilah , Bartholomew Blaner , Gordon Taylor Davis , Jeffrey Haskell Derby , Joseph Franklin Garvey , Malcolm Scott Ware , Hua Ye
发明人： Youseff Abdelilah , Bartholomew Blaner , Gordon Taylor Davis , Jeffrey Haskell Derby , Joseph Franklin Garvey , Malcolm Scott Ware , Hua Ye
IPC分类号： G06F13/16 , G06F15/163
CPC分类号： G06F13/28
摘要： A method, computer program product and system for facilitating inter-digital signal processing (DSP) data communications. A direct memory access (DMA) controller may be configured to facilitate transfers of data between a first and a second DSP processor core coupled to the DMA controller. The DMA controller may read a data structure, referred to as a “buffer descriptor block,” to perform the data transfer. The buffer descriptor block may store both a source address and a destination address indicating where the data is to be retrieved and stored. The buffer descriptor block may further store a value, e.g., number of bytes, indicating a size of the data to be transferred. The DMA controller may then transfer the data located at the source address in the first DSP processor core, with a size, e.g., number of bytes, indicated from the buffer descriptor block, to the destination address in the second DSP processor core.
摘要翻译：一种用于促进数字间数字信号处理（DSP）数据通信的方法，计算机程序产品和系统。直接存储器访问（DMA）控制器可以被配置为便于在耦合到DMA控制器的第一和第二DSP处理器核之间传输数据。 DMA控制器可以读取被称为“缓冲器描述符块”的数据结构来执行数据传送。缓冲器描述符块可以存储指示要检索和存储数据的源地址和目的地址。缓冲器描述符块还可以存储指示要传送的数据的大小的值，例如字节数。然后，DMA控制器可以将位于第一DSP处理器核心中的源地址处的数据以从缓冲器描述符块指示的大小（例如，字节数）传送到第二DSP处理器核心中的目的地地址。

5. 发明授权

US06986122B2 IF statement having an expression setup clause to be utilized in structured assembly language programming 失效
标题翻译： IF语句具有用于结构化汇编语言编程中的表达式设置子句
公开(公告)号：US06986122B2
公开(公告)日：2006-01-10
申请号：US09876366
申请日：2001-06-07
申请人： Joseph Franklin Garvey
发明人： Joseph Franklin Garvey
IPC分类号： G06F9/44
CPC分类号： G06F8/427
摘要： A state machine for an assembler capable of processing structured assembly language is disclosed. The state machine for an assembler capable of processing structured assembly language IF constructs includes five states, namely, an IF state, an ELSE state, an END—IF state, an ELSE—IF state, and a SETUP—IF state. In response to recognizing a SETUP—IF clause during the IF state or the ELSE—IF state, the process transitions to the SETUP—IF state. In response to recognizing an ELSE—IF clause during the SETUP—IF state, the process transitions to the ELSE—IF state.
摘要翻译：公开了一种能够处理结构化汇编语言的汇编器的状态机。用于能够处理结构化汇编语言IF构造的汇编器的状态机包括五个状态，即IF状态，ELSE状态，END IF状态，ELSE IF状态，和一个SETUP _{- IF状态。响应于在IF状态或ELSE IF状态期间识别SETUP IF子句，则该过程转换到SETUP _{- IF状态。响应于在SETUP IF状态期间识别ELSE IF子句，过程转换到ELSE _{- IF状态。}}}

6. 发明授权

US06374338B1 Method for performing configuration tasks prior to and including memory configuration within a processor-based system 失效
标题翻译：在基于处理器的系统之前执行配置任务并包括存储器配置的方法
公开(公告)号：US06374338B1
公开(公告)日：2002-04-16
申请号：US09344051
申请日：1999-06-25
申请人： Joseph Franklin Garvey
发明人： Joseph Franklin Garvey
IPC分类号： G06F1300
CPC分类号： G06F9/4403 , G06F12/0802 , G06F2212/2515
摘要： A method for performing configuration tasks prior to and including memory configuration within a processor based system is disclosed. A memory location is first reserved by a basic input/output system (BIOS) firmware for each individual BIOS task. A target routine is then performed using the reserved memory location by the BIOS firmware. The target routine is designed to perform a specific BIOS task. Finally, the reserved memory location is released by the BIOS firmware, after the target routine has been successfully completed.
摘要翻译：公开了一种在基于处理器的系统之前执行配置任务并包括存储器配置的方法。存储器位置首先由用于每个单独BIOS任务的基本输入/输出系统（BIOS）固件保留。然后使用BIOS固件的保留的存储器位置执行目标程序。目标程序被设计为执行特定的BIOS任务。最后，在目标程序成功完成后，BIOS固件会释放保留的内存位置。

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