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1. 发明授权

US4785423A Current limited epld array 失效
标题翻译：当前有限的epld数组
公开(公告)号：US4785423A
公开(公告)日：1988-11-15
申请号：US5927
申请日：1987-01-22
申请人： Joseph A. Skupnjak , Abid Asghar , Kirby S. Hallenbeck
发明人： Joseph A. Skupnjak , Abid Asghar , Kirby S. Hallenbeck
IPC分类号： G11C17/00 , G11C16/06 , G11C16/24 , H03K19/177 , G11C7/00 , G11C11/34
CPC分类号： G11C16/24
摘要： An improved architecture for an EPROM PAL utilizing two bit lines is disclosed. The drains of the EPROM cells of a given column of an array are coupled together to a first bit line. The first line is coupled to a sensing circuit. The sources of the EPROM cells are coupled together to a second bit line which is then coupled through a current limiting transistor. The gate of the transistor is coupled to the first bit line to receive a feedback signal for controlling the current on the bit lines. The current limiting feature provides for shorter transition periods between "on" and "off" states which results in an improved speed performance of the device.
摘要翻译：公开了一种利用两位线的EPROM PAL的改进架构。阵列的给定列的EPROM单元的漏极耦合到第一位线。第一行耦合到感测电路。 EPROM单元的源极耦合到第二位线，然后通过限流晶体管耦合。晶体管的栅极耦合到第一位线以接收用于控制位线上的电流的反馈信号。电流限制功能提供“开”和“关”状态之间较短的过渡周期，这导致器件的速度性能得到改善。

2. 发明授权

US4803659A EPROM latch circuit 失效
标题翻译： EPROM锁存电路
公开(公告)号：US4803659A
公开(公告)日：1989-02-07
申请号：US5925
申请日：1987-01-22
申请人： Kirby S. Hallenbeck
发明人： Kirby S. Hallenbeck
IPC分类号： G11C17/00 , G11C16/06 , G11C16/20 , G11C16/26 , G11C7/00 , G11C11/34 , G11C11/40
CPC分类号： G11C16/20 , G11C16/26
摘要： A latch circuit provides for a reading of a state of an EPROM cell and retains that state after the reading sequence is completed. The memory state of the EPROM is inputted to a NOR gate during a power on reset condition. The output of the NOR gate is fed back through an inverter to the input of the NOR gate, such that when the EPROM is deactivated, the input of the NOR gate is latched to the previous EPROM memory state.
摘要翻译：锁存电路提供对EPROM单元的状态的读取并且在读取顺序完成之后保持该状态。在上电复位条件期间，EPROM的存储状态被输入到或非门。 NOR门的输出通过反相器反馈到NOR门的输入，使得当EPROM被禁用时，NOR门的输入被锁存到先前的EPROM存储器状态。

3. 发明授权

US4761647A Eprom controlled tri-port transceiver 失效
标题翻译： Eprom控制三端口收发器
公开(公告)号：US4761647A
公开(公告)日：1988-08-02
申请号：US34846
申请日：1987-04-06
申请人： Kirby S. Hallenbeck , Lawrence S. Palley
发明人： Kirby S. Hallenbeck , Lawrence S. Palley
IPC分类号： H03K17/62 , H03K17/693 , H04Q11/04 , H04J3/04
CPC分类号： H03K17/62 , H03K17/693
摘要： A tri-port transceiver for receiving, switching and transmitting digital information among its ports. An input to each port is coupled to a multiplexer of each other port, wherein the multiplexer of each other port, wherein the multiplexers provide the switching of signals onto other ports. A buffer and a latch are used to couple each input port signal to the multiplexers, and a driver coupled to the multiplexer provides transmission of the selected signal from the multiplexer. An EPROM based PLA operates as a programmable state machine to generate control signals to the tri-port transceiver. In one embodiment, a programmable output impedance driver is used.
摘要翻译：用于在其端口之间接收，切换和传输数字信息的三端口收发器。每个端口的输入耦合到彼此端口的多路复用器，其中每个其他端口的多路复用器，其中多路复用器提供信号到其它端口的切换。缓冲器和锁存器用于将每个输入端口信号耦合到多路复用器，并且耦合到多路复用器的驱动器提供来自多路复用器的所选信号的传输。基于EPROM的PLA作为可编程状态机操作，以产生对三端口收发器的控制信号。在一个实施例中，使用可编程输出阻抗驱动器。

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