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1. 发明授权

US6040995A Method of operating a storage cell arrangement 失效
标题翻译：操作存储单元布置的方法
公开(公告)号：US6040995A
公开(公告)日：2000-03-21
申请号：US230614
申请日：1999-01-28
申请人： Hans Reisinger , Ulrike Gruning , Hermann Wendt , Reinhard Stengl , Volker Lehmann , Josef Willer , Martin Franosch , Herbert Schafer , Wolfgang Krautschneider , Franz Hofmann , Thomas Bohm
发明人： Hans Reisinger , Ulrike Gruning , Hermann Wendt , Reinhard Stengl , Volker Lehmann , Josef Willer , Martin Franosch , Herbert Schafer , Wolfgang Krautschneider , Franz Hofmann , Thomas Bohm
IPC分类号： H01L21/8247 , H01L29/51 , H01L29/788 , H01L29/792 , H01L27/02
CPC分类号： H01L29/513 , H01L29/518 , H01L29/792
摘要： For the operation of a memory cell arrangement with MOS transistors as memory cells that comprise a dielectric triple layer (5) with a first silicon oxide layer (51), a silicon nitride layer (52) and a second silicon oxide layer (53) as gate dielectric, whereby the silicon oxide layers are respectively at least 3 nm thick, a first cutoff voltage value is allocated to a first logical value and a second cutoff voltage value of the MOS transistor is allocated to a second logical value for storing digital data. The information stored in the memory cell can be modified by applying corresponding voltage levels, although a complete removal of charge stored in the silicon nitride layer is not possible because of the thickness of the silicon oxide layers. What is exploited when modifying the cutoff voltage is that the electrical field in the dielectric triple layer is distorted by charge stored in the silicon nitride layer.
摘要翻译： PCT No.PCT / DE97 / 01601 Sec。 371日期1999年1月28日 102（e）1999年1月28日PCT PCT 1997年7月29日PCT公布。出版物WO98 / 06140 日期1998年2月12日对于具有MOS晶体管的存储单元布置的操作，作为包含具有第一氧化硅层（51）的介电三层（5）的存储单元，具有氮化硅层（52）和第二氧化硅层（53）作为栅极电介质，由此氧化硅层分别为至少3nm厚，将第一截止电压值分配给第一逻辑值，并将MOS晶体管的第二截止电压值分配给第二逻辑值用于存储数字数据。存储在存储单元中的信息可以通过施加相应的电压电平来修改，尽管由于氧化硅层的厚度，不可能完全去除存储在氮化硅层中的电荷。当修改截止电压时，利用的是电介质三层中的电场由存储在氮化硅层中的电荷而失真。

2. 发明授权

US5866452A Process for producing a silicon capacitor 失效
标题翻译：硅电容器的制造方法
公开(公告)号：US5866452A
公开(公告)日：1999-02-02
申请号：US750942
申请日：1997-02-10
申请人： Josef Willer , Hermann Wendt , Herbert Schafer
发明人： Josef Willer , Hermann Wendt , Herbert Schafer
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8242
CPC分类号： H01L28/82
摘要： To produce a silicon capacitor, hole apertures at whose surface a conductive zone (40) is formed by doping and whose surface is provided with a dielectric layer (6) and a conductive layer (7) are generated in an n-doped silicon substrate (1). To compensate for mechanical strains in the silicon substrate (1) brought about by the doping of the conductive zone (40), the conductive zone (40) is additionally doped with germanium which is outdiffused from a germanium-doped layer.
摘要翻译： PCT No.PCT / DE95 / 01036 Sec。 371日期1997年2月10日 102（e）1997年2月10日PCT PCT 1995年8月7日PCT公布。出版物WO96 / 05620 日期1996年2月22日为了制造硅电容器，在其表面上通过掺杂形成导电区（40）的孔径，并且其表面上设置有电介质层（6）和导电层（7），在n 掺杂的硅衬底（1）。为了补偿由于导电区（40）的掺杂而导致的硅衬底（1）中的机械应变，导电区（40）另外掺有锗，其从锗掺杂层向外扩散。

3. 发明授权

US06194765B1 Integrated electrical circuit having at least one memory cell and method for fabricating it 有权
标题翻译：具有至少一个存储单元的集成电路及其制造方法
公开(公告)号：US06194765B1
公开(公告)日：2001-02-27
申请号：US09313433
申请日：1999-05-17
申请人： Hans Reisinger , Reinhard Stengl , Ulrike Grüning , Volker Lehmann , Hermann Wendt , Josef Willer , Martin Franosch , Herbert Schäfer
发明人： Hans Reisinger , Reinhard Stengl , Ulrike Grüning , Volker Lehmann , Hermann Wendt , Josef Willer , Martin Franosch , Herbert Schäfer
IPC分类号： H01L2976
CPC分类号： H01L27/11 , H01L27/1104 , Y10S257/903
摘要： An integrated electrical circuit has at least one memory cell, in which the memory cell is disposed in the region of a surface of a semiconductor substrate. The memory cell contains at least two inverters that are electrically connected to one another. The inverters each contain two complementary MOS transistors having a source, a drain and a channel, the channels of the complementary MOS transistors having different conductivity types. According to the invention, the integrated electrical circuit is constructed in such a way that the inverters are disposed perpendicularly to the surface of the semiconductor substrate. The source, the drain and the channel of the complementary MOS transistors are formed by layers which lie one on top of the other and are disposed in such a way that the complementary MOS transistors are situated one above the other. The invention furthermore relates to a method for fabricating the integrated electrical circuit.
摘要翻译：集成电路具有至少一个存储单元，其中存储单元设置在半导体衬底的表面的区域中。存储单元包含彼此电连接的至少两个反相器。反相器各自包含具有源极，漏极和沟道的两个互补MOS晶体管，所述互补MOS晶体管的沟道具有不同的导电类型。根据本发明，集成电路被构造成使得逆变器垂直于半导体衬底的表面设置。互补MOS晶体管的源极，漏极和沟道由层叠在另一个之上的层构成，并且以互补的MOS晶体管彼此上下的方式设置。本发明还涉及一种用于制造集成电路的方法。

4. 发明授权

US6165835A Method for producing a silicon capacitor 失效
标题翻译：硅电容器的制造方法
公开(公告)号：US6165835A
公开(公告)日：2000-12-26
申请号：US341937
申请日：1999-07-20
申请人： Hermann Wendt , Hans Reisinger , Andreas Spitzer , Reinhard Stengl , Ulrike Gruning , Josef Willer , Wolfgang Honlein , Volker Lehmann
发明人： Hermann Wendt , Hans Reisinger , Andreas Spitzer , Reinhard Stengl , Ulrike Gruning , Josef Willer , Wolfgang Honlein , Volker Lehmann
IPC分类号： H01L27/04 , H01L21/334 , H01L21/822 , H01L21/8242 , H01L29/94
CPC分类号： H01L27/10861 , H01L29/66181 , Y10S438/96
摘要： In producing a silicon capacitor, hole structures (2) are created in a silicon substrate (1), at the surface of which structures a conductive zone (3) is created by doping and whose surface is provided with a dielectric layer (4) and a conductive layer (5), without filling the hole structures (2). To compensate mechanical strains upon the silicon substrate (1) which are effected by the doping of the conductive zone (3), a conformal auxiliary layer (6) is formed on the surface of the conductive layer (5), which auxiliary layer is under a compressive mechanical stress.
摘要翻译： PCT No.PCT / DE98 / 00089 Sec。 371日期1999年7月20日 102（e）1999年7月20日PCT 1998年1月12日PCT PCT。出版物WO98 / 32166 日期1998年7月23日在制造硅电容器中，在硅衬底（1）中形成孔结构（2），其表面通过掺杂形成导电区（3），并且其表面设置有电介质层（4）和导电层（5），而不填充孔结构（2）。为了补偿通过掺杂导电区（3）实现的硅衬底（1）上的机械应变，在导电层（5）的表面上形成共形辅助层（6），该辅助层在下面压缩机械应力。

5. 发明授权

US5347696A Method for manufacturing a multi-layer capacitor 失效
标题翻译：多层电容器的制造方法
公开(公告)号：US5347696A
公开(公告)日：1994-09-20
申请号：US164719
申请日：1993-12-10
申请人： Josef Willer , Hermann Wendt , Hans Reisinger
发明人： Josef Willer , Hermann Wendt , Hans Reisinger
IPC分类号： C23F4/00 , H01G4/30 , H01L21/822 , H01L27/04 , H01G4/10
CPC分类号： H01G4/306 , Y10T29/435
摘要： For manufacturing a multi-layer capacitor, a layer structure (2, 3, 4) is applied onto a substrate (1), said layer structure comprising conductive layers (2, 4) and dielectric layers (3) in alternation and successive conductive layers (2, 4) therein being respectively formed of one of two different materials which are selectively etchable relative to one another. Two openings (6, 8) are produced in the layer structure (2, 3, 4), whereby under-etchings (21, 41 ) are formed in the first opening (6) by selective etching of the one material and are formed in the second opening (8) by selective etching of the other material, so that only the conductive layers (2, 4) of the non-etched material respectively adjoin contacts (91, 92) introduced into the openings (6, 8).
摘要翻译：为了制造多层电容器，将层结构（2,3,4）施加到衬底（1）上，所述层结构交替包括导电层（2,4）和电介质层（3），并且连续导电层（2,4）分别由可相对于彼此选择性地蚀刻的两种不同材料之一形成。在层结构（2,3,4）中产生两个开口（6,8），由此通过选择性蚀刻该一种材料形成在第一开口（6）中的下蚀刻（21,41），并形成在所述第二开口（8）通过选择性蚀刻所述另一材料，使得仅所述非蚀刻材料的所述导电层（2,4）分别与引入所述开口（6,8）的触点（91,92）相邻。

6. 发明授权

US6033534A Method for producing an Al-containing layer with a planar surface on a substrate having hole structures with a high aspect ratio in the surface 失效
标题翻译：在具有在表面上具有高纵横比的孔结构的基板上制造具有平坦表面的含Al层的方法
公开(公告)号：US6033534A
公开(公告)日：2000-03-07
申请号：US54200
申请日：1993-04-30
申请人： Josef Willer , Hermann Wendt , Volker Lehmann
发明人： Josef Willer , Hermann Wendt , Volker Lehmann
IPC分类号： H01L21/28 , H01L21/285 , H01L21/3205 , H01L21/334 , C23C14/34
CPC分类号： H01L29/66181 , H01L21/28512
摘要： A method for producing an Al-containing layer having a planar surface onto a substrate having hole structures with high aspect ratios formed in the surface of the substrate, wherein the Al-containing layer is applied in a sputtering process during which the substrate is held at an elevated temperature and the sputtering process is implemented at a pressure between 1.3.times.10.sup.-2 Pa and 13 Pa and at a low partial gas pressure. The substrate can be held at a temperature between approximately 400.degree. C. and 500.degree. C. during the sputtering process. A partial residual gas pressure of less than 1.3.times.10.sup.-5 PA can prevail in the vacuum. An intermediate layer of pure titanium and a barrier layer of TiN can be directly deposited onto the substrate and the Al-containing layer can then be applied onto this intermediate end barrier layer.
摘要翻译：一种在基板的表面形成具有高纵横比的孔结构的基板上的具有平坦表面的含Al层的方法，其中所述含Al层以基板保持在其中的溅射工艺升高的温度和溅射过程在1.3×10 -2 Pa至13 Pa之间的压力下和在低的部分气体压力下实施。在溅射过程中，衬底可保持在约400℃至500℃的温度。小于1.3×10-5PA的部分残余气体压力可以在真空中占优势。可以将纯钛的中间层和TiN的阻挡层直接沉积到衬底上，然后将含Al层施加到该中间阻挡层上。

7. 发明授权

US5306647A Method for manufacturing a solar cell from a substrate wafer 失效
标题翻译：从基板晶片制造太阳能电池的方法
公开(公告)号：US5306647A
公开(公告)日：1994-04-26
申请号：US998611
申请日：1992-12-30
申请人： Volker Lehmann , Reinhard Stengl , Hermann Wendt , Wolfgang Hoenlein , Josef Willer
发明人： Volker Lehmann , Reinhard Stengl , Hermann Wendt , Wolfgang Hoenlein , Josef Willer
IPC分类号： C25F3/12 , H01L21/3063 , H01L31/0352 , H01L31/047 , H01L31/18
CPC分类号： H01L31/1804 , H01L21/3063 , H01L31/03529 , H01L31/047 , Y02E10/547 , Y02P70/521
摘要： A self-supporting layer of n-doped monocrystalline silicon is stripped from a substrate wafer of n-doped, monocrystalline silicon by electrochemical etching for manufacturing a solar cell. Holes are formed in the substrate wafer by electrochemical etching, particularly in a fluoride-containing, acidic electrolyte wherein the substrate wafer is connected as an anode. When a depth of the holes that essentially corresponds to the thickness of the self-supporting layer is reached, the process parameters of the etching are modified such that the self-supporting layer is stripped as a consequence of the holes growing together. The solar cell is manufactured from the self-supporting layer, and the method can be applied repeatedly on the same substrate wafer for stripping a plurality of self-supporting layers.
摘要翻译：通过用于制造太阳能电池的电化学蚀刻，从n掺杂的单晶硅的衬底晶片剥离n掺杂单晶硅的自支撑层。通过电化学蚀刻，特别是在其中衬底晶片作为阳极连接的含氟化物的酸性电解质中，在衬底晶片中形成孔。当达到基本上对应于自支撑层的厚度的孔的深度时，蚀刻的工艺参数被修改，使得自支撑层由于孔一起生长而被剥离。该太阳能电池由自支撑层制造，并且可以在相同的基板晶片上重复地施加该方法以剥离多个自支撑层。

8. 发明授权

US5500385A Method for manufacturing a silicon capacitor by thinning 失效
标题翻译：通过减薄制造硅电容器的方法
公开(公告)号：US5500385A
公开(公告)日：1996-03-19
申请号：US451534
申请日：1995-05-26
申请人： Hermann Wendt , Josef Willer , Hans Reisinger , Volker Lehmann
发明人： Hermann Wendt , Josef Willer , Hans Reisinger , Volker Lehmann
IPC分类号： H01L27/04 , H01L21/225 , H01L21/334 , H01L21/822 , H01L21/762
CPC分类号： H01L29/66181 , Y10S438/924 , Y10S438/928 , Y10S438/977
摘要： For manufacturing a silicon capacitor, hole openings are produced in an n-doped silicon substrate, a p.sup.+ -doped region is formed at the surface thereof and this surface is provided with a dielectric layer together with a conductive layer. The silicon substrate is thinned with an etching proceeding from the back side, this etching attacking silicon selectively to p.sup.+ -doped silicon and therefore stopping when the p.sup.+ -doped region is reached.
摘要翻译：为了制造硅电容器，在n掺杂硅衬底中产生孔开口，在其表面形成p +掺杂区域，并且该表面与导电层一起设置介电层。硅衬底通过从背面进行的蚀刻变薄，该蚀刻选择性地攻击到p +掺杂的硅，因此当达到p +掺杂区域时停止。

9. 发明授权

US6140177A Process of forming a semiconductor capacitor including forming a hemispherical grain statistical mask with silicon and germanium 有权
标题翻译：形成半导体电容器的工艺包括用硅和锗形成半球形晶粒统计掩模
公开(公告)号：US6140177A
公开(公告)日：2000-10-31
申请号：US242153
申请日：1999-02-09
申请人： Herbert Schafer , Martin Franosch , Reinhard Stengl , Volker Lehmann , Hans Reisinger , Hermann Wendt
发明人： Herbert Schafer , Martin Franosch , Reinhard Stengl , Volker Lehmann , Hans Reisinger , Hermann Wendt
IPC分类号： H01L21/02 , H01L21/8242
CPC分类号： H01L28/92 , Y10S438/947
摘要： For manufacturing a capacitor that is essentially suited for DRAM arrangements, column structures that form an electrode of the capacitor are etched upon employment of a statistical mask that is produced without lithographic steps by nucleus formation of Si/Ge and subsequent selective epitaxy. Structure sizes below 100 nm can be realized in the statistical mask. Surface enlargement factors up to 60 are thus achieved.
摘要翻译： PCT No.PCT / DE97 / 01408 Sec。 371日期1999年2月9日 102（e）1999年2月9日PCT PCT 1997年7月3日PCT公布。出版物WO98 / 07184 日期1998年2月19日为了制造基本上适用于DRAM布置的电容器，使用形成电容器电极的列结构被蚀刻，使用统计掩模，其通过Si / Ge的核形成并且随后选择性地产生无平版印刷步骤外延在统计掩模中可以实现小于100nm的结构尺寸。从而达到高达60的表面增大因子。

10. 发明授权

US6127220A Manufacturing method for a capacitor in an integrated storage circuit 有权
标题翻译：集成存储电路中电容器的制造方法
公开(公告)号：US6127220A
公开(公告)日：2000-10-03
申请号：US312571
申请日：1999-05-14
申请人： Gerrit Lange , Martin Franosch , Volker Lehmann , Hans Reisinger , Herbert Schafer , Reinhard Stengl , Hermann Wendt
发明人： Gerrit Lange , Martin Franosch , Volker Lehmann , Hans Reisinger , Herbert Schafer , Reinhard Stengl , Hermann Wendt
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817
摘要： On a carrier a layer sequence is applied which contains alternatingly layers made of a first conducting material and a second material in which both materials are different from a carrier material. An opening is made in the layer sequence, which is filled with a conducting material so that a central supporting structure is produced. Then the layer sequence is structured corresponding to the dimensions of a capacitor and the layers made of the second material are removed selectively, so that a first capacitor electrode is formed. The layer sequence may have especially p.sup.+ -/p.sup.- silicon layers or silicon/germanium layers. An etch-stop layer can also be incorporated as the lowest or second-lowest layer.
摘要翻译：在载体上施加层序列，其包含由第一导电材料和第二材料制成的交替层，其中两种材料都不同于载体材料。在层序列中形成开口，其中填充有导电材料，从而产生中心支撑结构。然后根据电容器的尺寸构造层序列，并且选择性地去除由第二材料制成的层，从而形成第一电容器电极。层序列可以具有特别的p + - / p-硅层或硅/锗层。也可以将蚀刻停止层作为最低层或第二层加入。

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