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    • 1. 发明授权
    • Front-end system for processing composite wideband signals and method for utilizing same
    • 用于处理复合宽带信号的前端系统及其利用方法
    • US08391316B2
    • 2013-03-05
    • US12590341
    • 2009-11-06
    • Jose Ignacio GorosteguiStephen Edward Krafft
    • Jose Ignacio GorosteguiStephen Edward Krafft
    • H04H20/28H04J1/02H04N7/20
    • H04B1/06H04B1/0057H04N7/20
    • According to one exemplary embodiment, a front-end system for processing a composite wideband signal comprises a pre-receiving unit including a multiplexer for separating the composite wideband signal into a plurality of filtered signals. The front-end system further comprises a plurality of discrete frequency band outputs corresponding to the plurality of filtered signals, and a tuner/down-converter coupled to at least one of the plurality of discrete frequency band outputs. In one embodiment, the pre-receiving unit of the front-end system further comprises a second multiplexer for separating at least one of the plurality of filtered signals into a second plurality of filtered signals. In one embodiment, the pre-receiving unit may further comprise a low noise amplifier for processing at least one of the plurality of filtered signals before it is input to the second multiplexer.
    • 根据一个示例性实施例,用于处理复合宽带信号的前端系统包括预接收单元,其包括用于将复合宽带信号分离成多个滤波信号的多路复用器。 前端系统还包括对应于多个滤波信号的多个离散频带输出,以及耦合到多个离散频带输出中的至少一个的调谐器/下变频器。 在一个实施例中,前端系统的预接收单元还包括第二多路复用器,用于将多个滤波信号中的至少一个分离成第二多个滤波信号。 在一个实施例中,预接收单元还可以包括低噪声放大器,用于在多个滤波信号被输入到第二多路复用器之前处理多个滤波信号中的至少一个。
    • 2. 发明申请
    • Front-end system for processing composite wideband signals and method for utilizing same
    • 用于处理复合宽带信号的前端系统及其利用方法
    • US20110110385A1
    • 2011-05-12
    • US12590341
    • 2009-11-06
    • Jose Ignacio GorosteguiStephen Edward Krafft
    • Jose Ignacio GorosteguiStephen Edward Krafft
    • H04J1/02
    • H04B1/06H04B1/0057H04N7/20
    • According to one exemplary embodiment, a front-end system for processing a composite wideband signal comprises a pre-receiving unit including a multiplexer for separating the composite wideband signal into a plurality of filtered signals. The front-end system further comprises a plurality of discrete frequency band outputs corresponding to the plurality of filtered signals, and a tuner/down-converter coupled to at least one of the plurality of discrete frequency band outputs. In one embodiment, the pre-receiving unit of the front-end system further comprises a second multiplexer for separating at least one of the plurality of filtered signals into a second plurality of filtered signals. In one embodiment, the pre-receiving unit may further comprise a low noise amplifier for processing at least one of the plurality of filtered signals before it is input to the second multiplexer.
    • 根据一个示例性实施例,用于处理复合宽带信号的前端系统包括预接收单元,其包括用于将复合宽带信号分离成多个滤波信号的多路复用器。 前端系统还包括对应于多个滤波信号的多个离散频带输出,以及耦合到多个离散频带输出中的至少一个的调谐器/下变频器。 在一个实施例中,前端系统的预接收单元还包括第二多路复用器,用于将多个滤波信号中的至少一个分离成第二多个滤波信号。 在一个实施例中,预接收单元还可以包括低噪声放大器,用于在多个滤波信号被输入到第二多路复用器之前处理多个滤波信号中的至少一个。
    • 7. 发明授权
    • Sample rate reduction in data communication receivers
    • 数据通信接收机采样率降低
    • US07559076B2
    • 2009-07-07
    • US10184770
    • 2002-06-28
    • Tommy YuSteven JaffeStephen Edward Krafft
    • Tommy YuSteven JaffeStephen Edward Krafft
    • H04N5/445
    • H04N21/437H04L27/3881H04N7/173H04N21/2383H04N21/239H04N21/41407H04N21/4382H04N21/6131H04N21/6181
    • Sample rate reduction in data communication receivers. Digital sampling of analog data is performed using a reduced sample rate. The reduction factor may be any number of factors including a factor that divides the sample rate by a factor of two. The reduction of the sampling frequency is from a sampling frequency that is greater than twice the highest frequency component in an analog input signal. These analog input signals may be I and Q streams in certain embodiments. A digital interpolation filter may be employed to increase (up-convert) the sample rate of a digital signal before it is input to a VID filter that is used to recover the transmitted symbols from the over-sampled data stream. In this embodiment, this technique allows a front end of a communication receiver to be clocked at a lower sampling rate without affecting the performance of the VID filter.
    • 数据通信接收机采样率降低。 使用降低的采样率进行模拟数据的数字采样。 减少因子可以是任何数量的因素,包括将采样率除以因子2的因子。 采样频率的降低来自大于模拟输入信号中最高频率分量的两倍的采样频率。 在某些实施例中,这些模拟输入信号可以是I和Q流。 可以采用数字内插滤波器来增加(上转换)数字信号的采样速率,然后再将其输入到用于从过采样数据流中恢复发送符号的VID滤波器。 在该实施例中,该技术允许通信接收器的前端以较低的采样率被计时,而不影响VID滤波器的性能。
    • 8. 发明授权
    • Interleaver for iterative decoder
    • 交织器用于迭代解码器
    • US07360040B2
    • 2008-04-15
    • US11231635
    • 2005-09-21
    • Hiroshi SuzukiStephen Edward Krafft
    • Hiroshi SuzukiStephen Edward Krafft
    • G06F12/00G06F13/00G06F13/28
    • H04L1/005H03M13/258H03M13/27H03M13/2767H03M13/2771H03M13/2785H03M13/2957H03M13/4161H04L1/0066H04L1/0068H04L1/0071
    • Interleaver for iterative decoder. A memory management scheme allows for single plane/single port memory devices to be used by the interleaver. The design is adaptable to soft-in soft-out (SISO) decoders that perform iterative decoding. The interleaver may be implemented within communication devices that implement two distinct SISOs that operate cooperatively or within communication devices that employ a single SISO (in a recycled embodiment) that functionally performs the analogous decoding operations that would be performed by the two distinct SISO implementation. The use of single plane/single port memory devices by the interleaver allows for a great deal of savings from many perspectives: the sizes of the required interleaver memory and the interleaver pattern memory are both cut in half using this approach, and a cost savings may also be realized, in that, cheaper, slower memories may be used since each respective interleaver memory is read only every other cycle.
    • 交织器用于迭代解码器。 存储器管理方案允许单平面/单端口存储器件由交织器使用。 该设计适用于执行迭代解码的软进软(SISO)解码器。 交织器可以在实现两个不同的SISO的通信设备中实现,这两个SISO协作地或在使用在功能上执行由两个不同的SISO实现执行的类似解码操作的单个SISO(在回收的实施例中)的通信设备内。 通过交织器使用单平面/单端口存储器件允许从许多角度大量节省:使用这种方法所需的交织器存储器和交织器模式存储器的尺寸都被削减了一半,并且可以节省成本 也可以实现,由于每个相应的交织器存储器仅在每隔一个周期读取,所以可以使用更便宜的较慢的存储器。