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    • 7. 发明授权
    • Page composition system
    • 页面组成系统
    • US06856421B1
    • 2005-02-15
    • US09509753
    • 1997-09-30
    • Gideon AmirNoam ShahamYoram ArnonLenny Ridel
    • Gideon AmirNoam ShahamYoram ArnonLenny Ridel
    • B41J5/30G06T1/00G06T11/60G06F3/12G06F12/00
    • G06T11/60
    • A page composition method for composing a page from elements in pixelized form for bit-mapping or half-toning prior to printing including; (a) determining the positions of the elements on a printed page; (b) dividing the page into bands; (c) serially transferring pixel data values for sections of bands corresponding to the portions of respective elements in a band, seriatim to a buffer memory, wherein the data from the portion of one element in a band is completely read prior to reading data corresponding to the portion of a second element in the band; (d) writing the data to a buffer memory as it is read; and (e) transferring the data from the buffer memory when all the data corresponding to all portions of all elements in the band is written in the buffer memory.
    • 一种页面合成方法,用于从打印前的位映像或半色调的像素化形式的元素构成页面,包括: (a)确定印刷页上元素的位置; (b)将页面划分为乐队; (c)将对应于频带中的各个元件的部分的频带的像素数据值串行传送到缓冲存储器,其中来自频带中的一个元素的部分的数据在读取对应于数据的数据之前被完全读取 所述带中的第二元素的部分; (d)读取数据到缓冲存储器; 并且(e)当对应于所述频带中的所有元素的所有部分的所有数据都写入缓冲存储器时,从缓冲存储器传送数据。
    • 8. 发明授权
    • Digital to analog converter utilizing pulse width modulation
    • 采用脉冲宽度调制的数模转换器
    • US4590457A
    • 1986-05-20
    • US563720
    • 1983-12-20
    • Gideon Amir
    • Gideon Amir
    • H03M1/82H03M1/00
    • H03M1/0872
    • A pulse width digital to analog converter is constructed which provides an output clock rate that is a multiple of the input sampling rate. In one embodiment a latch is used to store N-bit digital word representing the analog signal value to be generated. (N-K) of the most significant bits are stored in a counter which decrements its count in response to a clock signal. A plurality of least significant bits of said digital word stored in said latch are applied to a logic circuit. A ring counter is utilized to indicate which section of the output signal is currently being generated. The plurality of the least significant bits of the digital word stored in the latch, together with the output signals from the ring counter, are applied to said logic circuit, and the transition of the output signal of the digital to analog converter from a logical one to a logical zero is delayed, when required, to provide a slightly increased output pulse width in response to said plurality of least significant bits of said digital word, thereby maintaining or even increasing the resolution of the system.
    • 构造了一个脉宽数字到模拟转换器,其提供了输入采样率的倍数的输出时钟速率。 在一个实施例中,锁存器用于存储表示要生成的模拟信号值的N位数字字。 最高有效位的(N-K)存储在计数器中,该计数器响应于时钟信号递减其计数。 存储在所述锁存器中的所述数字字的多个最低有效位被施加到逻辑电路。 使用振铃计数器来指示当前正在生成输出信号的哪个部分。 存储在锁存器中的数字字的多个最低有效位与来自环形计数器的输出信号一起被施加到​​所述逻辑电路,并且数模转换器的输出信号从逻辑1转换 当需要时,逻辑零被延迟以响应于所述数字字的所述多个最低有效位而提供略微增加的输出脉冲宽度,由此维持或甚至提高系统的分辨率。