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1. 发明申请

US20070296935A1 Substrate having alignment marks and method of obtaining alignment information using the same 失效
标题翻译：具有对准标记的基板和使用其的获取对准信息的方法
公开(公告)号：US20070296935A1
公开(公告)日：2007-12-27
申请号：US11723362
申请日：2007-03-19
申请人： Joon-Sung Kim , Ji-Yong You
发明人： Joon-Sung Kim , Ji-Yong You
IPC分类号： G03B27/52 , G01B11/00
CPC分类号： G03F9/7084 , G03F9/7076 , G03F9/708
摘要： The alignment marks formed in a scribe line of a semiconductor substrate include at least one main mark, a first sub-mark and second sub-marks. The first sub-mark is formed at a central portion of the main mark. The second sub-marks are disposed symmetrically with respect to the first sub-mark and are used for detecting asymmetry of the main mark by measuring distances between respective side edges of the main mark and the first sub-mark, and by measuring respective side edges between the main mark and each of the second sub-marks. Alternatively, the alignment marks include main outer and inner marks and a sub-mark disposed in between the main outer and inner marks. In this case, the sub-mark is used for detecting asymmetry of the main mark by measuring distances between respective side edges of the main outer mark and the sub-mark, and by measuring respective side edges between the main inner mark and the sub-mark. Thus, accurate alignment information can be obtained regardless of whether the main mark was inadvertently formed as asymmetrical.
摘要翻译：形成在半导体衬底的划线中的对准标记包括至少一个主标记，第一子标记和第二子标记。第一子标记形成在主标记的中心部分。第二子标记相对于第一子标记对称设置，并且用于通过测量主标记的各个侧边缘与第一子标记之间的距离来检测主标记的不对称性，并且通过测量相应的侧边缘主标记和每个第二个子标记之间。或者，对准标记包括主外标和内标，以及设置在主外标和内标之间的子标记。在这种情况下，子标记用于通过测量主外标号和子标记的各侧边缘之间的距离来检测主标记的不对称性，并且通过测量主内标和子标记之间的相应侧边缘，标记。因此，无论主标记是否被无意地形成为不对称，都可以获得准确的对准信息。

2. 发明授权

US07602072B2 Substrate having alignment marks and method of obtaining alignment information using the same 失效
标题翻译：具有对准标记的基板和使用其的获取对准信息的方法
公开(公告)号：US07602072B2
公开(公告)日：2009-10-13
申请号：US11723362
申请日：2007-03-19
申请人： Joon-Sung Kim , Ji-Yong You
发明人： Joon-Sung Kim , Ji-Yong You
IPC分类号： H01L21/76
CPC分类号： G03F9/7084 , G03F9/7076 , G03F9/708
摘要： The alignment marks formed in a scribe line of a semiconductor substrate include at least one main mark, a first sub-mark and second sub-marks. The first sub-mark is formed at a central portion of the main mark. The second sub-marks are disposed symmetrically with respect to the first sub-mark and are used for detecting asymmetry of the main mark by measuring distances between respective side edges of the main mark and the first sub-mark, and by measuring respective side edges between the main mark and each of the second sub-marks. Alternatively, the alignment marks include main outer and inner marks and a sub-mark disposed in between the main outer and inner marks. In this case, the sub-mark is used for detecting asymmetry of the main mark by measuring distances between respective side edges of the main outer mark and the sub-mark, and by measuring respective side edges between the main inner mark and the sub-mark. Thus, accurate alignment information can be obtained regardless of whether the main mark was inadvertently formed as asymmetrical.
摘要翻译：形成在半导体衬底的划线中的对准标记包括至少一个主标记，第一子标记和第二子标记。第一子标记形成在主标记的中心部分。第二子标记相对于第一子标记对称设置，并且用于通过测量主标记的各个侧边缘与第一子标记之间的距离来检测主标记的不对称性，并且通过测量相应的侧边缘主标记和每个第二个子标记之间。或者，对准标记包括主外标和内标，以及设置在主外标和内标之间的子标记。在这种情况下，子标记用于通过测量主外标号和子标记的各侧边缘之间的距离来检测主标记的不对称性，并且通过测量主内标和子标记之间的相应侧边缘，标记。因此，无论主标记是否被无意地形成为不对称，都可以获得准确的对准信息。

3. 发明申请

US20070063317A1 Overlay key, method of forming the overlay key, semiconductor device including the overlay key and method of manufacturing the semiconductor device 审中-公开
标题翻译：覆盖键，形成覆盖键的方法，包括覆盖键的半导体器件和制造半导体器件的方法
公开(公告)号：US20070063317A1
公开(公告)日：2007-03-22
申请号：US11472376
申请日：2006-06-22
申请人： Dae-Joung Kim , Dae-Youp Lee , Ji-Yong You , Chun-Suk Suh , Do-Yul Yoo
发明人： Dae-Joung Kim , Dae-Youp Lee , Ji-Yong You , Chun-Suk Suh , Do-Yul Yoo
IPC分类号： H01L29/06 , H01L23/48 , H01L23/52 , H01L29/40 , H01L21/336 , H01L21/00
CPC分类号： H01L23/544 , G03F7/70633 , H01L29/665 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： An overlay key formed in a scribe lane and used to align a circuit pattern may include a lower overlay mark formed on a metal silicide layer directly in contact with a silicon substrate. A method of forming an overlay key in a scribe lane may include providing a silicon substrate, forming a metal silicide layer to be in direct contact with the silicon substrate, and forming a lower overlay mark on the metal silicide layer.
摘要翻译：形成在划线中并用于对齐电路图案的覆盖键可以包括形成在直接与硅衬底接触的金属硅化物层上的下覆盖标记。在划线中形成覆盖键的方法可以包括提供硅衬底，形成与硅衬底直接接触的金属硅化物层，以及在金属硅化物层上形成较低的重叠标记。

4. 发明申请

US20070026685A1 Mask structure, method of forming the mask structure, method of forming a pattern using the mask structure and method of forming contacts in a semiconductor device using the mask structure 审中-公开
标题翻译：掩模结构，形成掩模结构的方法，使用掩模结构形成图案的方法以及使用掩模结构在半导体器件中形成接触的方法
公开(公告)号：US20070026685A1
公开(公告)日：2007-02-01
申请号：US11481177
申请日：2006-07-06
申请人： Yong-Kug Bae , Ji-Yong You , Yong-Sun Ko , Seung-Won Seong
发明人： Yong-Kug Bae , Ji-Yong You , Yong-Sun Ko , Seung-Won Seong
IPC分类号： H01L21/302
CPC分类号： H01L21/32139 , H01L21/0332 , H01L21/0337 , H01L21/31144 , H01L21/76816
摘要： A mask structure may include a first mask pattern and a second mask pattern formed on an object. When the object includes a first material, the first and the second mask patterns may include a second material and a third material, respectively. The second mask pattern may have at least two openings that expose portions of the object adjacent to sides of the first mask pattern. Because the mask structure has the first and the second mask patterns, desired structures, for example, recesses, trenches, contact holes or patterns may be more precisely formed on or through the object. For example, the first mask pattern may protect the object in an etching process for forming contact holes so that the contact holes may not be connected to each other, for example, when the contact holes have bar shapes or line shapes.
摘要翻译：掩模结构可以包括形成在物体上的第一掩模图案和第二掩模图案。当物体包括第一材料时，第一和第二掩模图案可以分别包括第二材料和第三材料。第二掩模图案可以具有暴露邻近第一掩模图案的侧面的物体的部分的至少两个开口。由于掩模结构具有第一和第二掩模图案，所以可以更精确地形成所需的结构，例如凹槽，沟槽，接触孔或图案。例如，第一掩模图案可以在用于形成接触孔的蚀刻工艺中保护物体，使得接触孔可以不彼此连接，例如当接触孔具有条形或线形时。

5. 发明申请

US20080032208A1 Overlay mark and method of forming the same 有权
标题翻译：叠加标记和形成方法
公开(公告)号：US20080032208A1
公开(公告)日：2008-02-07
申请号：US11826745
申请日：2007-07-18
申请人： Dae-Joung Kim , Ji-Yong You , Hyun-Seok Lim
发明人： Dae-Joung Kim , Ji-Yong You , Hyun-Seok Lim
IPC分类号： G03F1/00
CPC分类号： G03F7/70633
摘要： An overlay mark may include a main overlay pattern and an auxiliary overlay pattern, wherein the main overlay pattern may have an opening exposing a substrate and the auxiliary overlay pattern may be formed in the opening. The auxiliary overlay pattern may be spaced apart from a sidewall of the main overlay pattern defining the opening. The thickness ratio of the auxiliary overlay pattern to the main overlay pattern may be about 0.05:1 to about 0.30:1. Accordingly, overlay accuracy measurements may be improved using the clearer overlay mark according to example embodiments.
摘要翻译：覆盖标记可以包括主覆盖图案和辅助覆盖图案，其中主覆盖图案可以具有暴露基板的开口，并且可以在开口中形成辅助覆盖图案。辅助覆盖图案可以与限定开口的主覆盖图案的侧壁间隔开。辅助覆盖图案与主覆盖图案的厚度比可以为约0.05:1至约0.30:1。因此，可以使用根据示例性实施例的更清晰的覆盖标记来改善覆盖精度测量。

6. 发明申请

US20070009838A1 Method of manufacturing a pattern structure and method of forming a trench using the same 审中-公开
标题翻译：图案结构的制造方法以及使用其形成沟槽的方法
公开(公告)号：US20070009838A1
公开(公告)日：2007-01-11
申请号：US11475913
申请日：2006-06-28
申请人： Ji-Yong You , Chun-Suk Suh , Hak Kim , Dae-Joung Kim , Kyoung-Yun Baek
发明人： Ji-Yong You , Chun-Suk Suh , Hak Kim , Dae-Joung Kim , Kyoung-Yun Baek
IPC分类号： G03F7/26
CPC分类号： G03F7/405 , H01L21/0334 , H01L21/3083
摘要： A method of manufacturing a pattern structure and a method of forming a trench using the same are provided. A mask pattern structure having mask patterns spaced apart from one another may be formed on a layer. The mask pattern structure may be divided into a first region having a first pattern density and a second region having a second pattern density higher than the first pattern density. The layer may be etched using the mask pattern structure as an etching mask to form first sidewalls positioned under the first region and second sidewalls positioned under the second region. The first sidewall may have a first profile that may be substantially vertical. The second sidewall may have a second profile of which an interval between the second sidewalls becomes narrower toward lower portions of the second sidewalls.
摘要翻译：提供了制造图案结构的方法和使用其形成沟槽的方法。具有彼此间隔开的掩模图案的掩模图案结构可以形成在层上。掩模图案结构可以被划分为具有第一图案密度的第一区域和具有高于第一图案密度的第二图案密度的第二区域。可以使用掩模图案结构蚀刻该层作为蚀刻掩模，以形成位于第一区域下方的第一侧壁和位于第二区域下方的第二侧壁。第一侧壁可以具有基本垂直的第一轮廓。第二侧壁可以具有第二轮廓，第二侧壁之间的间隔朝向第二侧壁的下部变窄。

7. 发明授权

US08339604B2 Substrate including alignment marks, methods of aligning wafers and fabricating semiconductors 有权
标题翻译：基板包括对准标记，对准晶圆的方法和制造半导体
公开(公告)号：US08339604B2
公开(公告)日：2012-12-25
申请号：US12656812
申请日：2010-02-17
申请人： Jun-Young Jang , Ji-Yong You
发明人： Jun-Young Jang , Ji-Yong You
IPC分类号： G01B11/00
CPC分类号： G03F9/7076
摘要： Provided is a substrate having an alignment mark, methods of aligning wafers and fabricating semiconductors. An alignment method of a wafer comprises providing a wafer on a wafer stage of a photolithography apparatus, irradiating light to the alignment mark, collecting reflected light from the alignment mark, analyzing optical information of the collected light, and determining a location of the wafer based on the analyzed optical information, wherein the wafer comprises a first surface having an alignment mark, the alignment mark including a first plurality of alignment patterns in a first row, and a second plurality of alignment patterns in a second row, the second plurality of alignment patterns being adjacent to the first plurality of alignment patterns, wherein the first plurality of alignment patterns are arranged in a row direction at a first pitch, and the second plurality of alignment patterns are arranged in the row direction at a second pitch different from the first pitch.
摘要翻译：提供了具有对准标记的基板，对准晶片的方法和制造半导体。晶片的对准方法包括在光刻设备的晶片台上设置晶片，向对准标记照射光，收集来自对准标记的反射光，分析所收集的光的光学信息，以及确定基于晶片的位置在所分析的光学信息上，其中所述晶片包括具有对准标记的第一表面，所述对准标记包括第一行中的第一多个对准图案和第二排中的第二多个对准图案，所述第二多个对准图案与第一多个对准图案相邻，其中第一多个对准图案以第一间距排列在行方向上，并且第二多个对准图案在行方向上以不同于第一间距的第二间距布置沥青。

8. 发明申请

US20100245825A1 Substrate including alignment marks, methods of aligning wafers and fabricating semiconductors 有权
标题翻译：基板包括对准标记，对准晶圆的方法和制造半导体
公开(公告)号：US20100245825A1
公开(公告)日：2010-09-30
申请号：US12656812
申请日：2010-02-17
申请人： Jun-Young Jang , Ji-Yong You
发明人： Jun-Young Jang , Ji-Yong You
IPC分类号： G01B11/27 , G01B11/14
CPC分类号： G03F9/7076
摘要： Provided is a substrate having an alignment mark, methods of aligning wafers and fabricating semiconductors. An alignment method of a wafer comprises providing a wafer on a wafer stage of a photolithography apparatus, irradiating light to the alignment mark, collecting reflected light from the alignment mark, analyzing optical information of the collected light, and determining a location of the wafer based on the analyzed optical information, wherein the wafer comprises a first surface having an alignment mark, the alignment mark including a first plurality of alignment patterns in a first row, and a second plurality of alignment patterns in a second row, the second plurality of alignment patterns being adjacent to the first plurality of alignment patterns, wherein the first plurality of alignment patterns are arranged in a row direction at a first pitch, and the second plurality of alignment patterns are arranged in the row direction at a second pitch different from the first pitch.
摘要翻译：提供了具有对准标记的基板，对准晶片的方法和制造半导体。晶片的对准方法包括在光刻设备的晶片台上设置晶片，向对准标记照射光，收集来自对准标记的反射光，分析所收集的光的光学信息，以及确定基于晶片的位置在所分析的光学信息上，其中所述晶片包括具有对准标记的第一表面，所述对准标记包括第一行中的第一多个对准图案和第二排中的第二多个对准图案，所述第二多个对准图案与第一多个对准图案相邻，其中第一多个对准图案以第一间距排列在行方向上，并且第二多个对准图案在行方向上以不同于第一间距的第二间距布置沥青。

9. 发明授权

US07736844B2 Overlay mark and method of forming the same 有权
标题翻译：叠加标记和形成方法
公开(公告)号：US07736844B2
公开(公告)日：2010-06-15
申请号：US11826745
申请日：2007-07-18
申请人： Dae-Joung Kim , Ji-Yong You , Hyun-Seok Lim
发明人： Dae-Joung Kim , Ji-Yong You , Hyun-Seok Lim
IPC分类号： G03F1/00 , H01L23/544
CPC分类号： G03F7/70633
摘要： An overlay mark may include a main overlay pattern and an auxiliary overlay pattern, wherein the main overlay pattern may have an opening exposing a substrate and the auxiliary overlay pattern may be formed in the opening. The auxiliary overlay pattern may be spaced apart from a sidewall of the main overlay pattern defining the opening. The thickness ratio of the auxiliary overlay pattern to the main overlay pattern may be about 0.05:1 to about 0.30:1. Accordingly, overlay accuracy measurements may be improved using the clearer overlay mark according to example embodiments.
摘要翻译：覆盖标记可以包括主覆盖图案和辅助覆盖图案，其中主覆盖图案可以具有暴露基板的开口，并且可以在开口中形成辅助覆盖图案。辅助覆盖图案可以与限定开口的主覆盖图案的侧壁间隔开。辅助覆盖图案与主覆盖图案的厚度比可以为约0.05:1至约0.30:1。因此，可以使用根据示例性实施例的更清晰的覆盖标记来改善覆盖精度测量。

10. 发明授权

US07732105B2 Photomask with overlay mark and method of fabricating semiconductor device 有权
标题翻译：具有覆盖标记的光掩模和制造半导体器件的方法
公开(公告)号：US07732105B2
公开(公告)日：2010-06-08
申请号：US11777863
申请日：2007-07-13
申请人： Do-Yul Yoo , Ji-Yong You , Joong-Sung Kim , Hyung-Joo Youn
发明人： Do-Yul Yoo , Ji-Yong You , Joong-Sung Kim , Hyung-Joo Youn
IPC分类号： G03F1/00 , G03F9/00
CPC分类号： G03F7/70633
摘要： Provided are a photomask and a method of fabricating a semiconductor device. The photomask includes a photomask substrate including a chip region and a scribe lane region, with an overlay mark formed in the scribe lane region. The overlay mark includes one or more sub-overlay marks. Each of the sub-overlay marks includes a plurality of unit regions sequentially connected to each other and having different widths, where the width of a given unit region is constant.
摘要翻译：提供了一种光掩模和一种制造半导体器件的方法。光掩模包括具有芯片区域和划线路区域的光掩模基板，在划线路区域形成有覆盖标记。覆盖标记包括一个或多个子覆盖标记。每个子覆盖标记包括彼此顺序连接并且具有不同宽度的多个单位区域，其中给定单位区域的宽度是恒定的。

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