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    • 1. 发明申请
    • RESISTOR-CAPACITOR OSCILLATION CIRCUIT CAPABLE OF ADJUSTING OSCILLATION FREQUENCY AND METHOD OF THE SAME
    • 调整振荡频率的电容器电容振荡电路及其方法
    • US20080100391A1
    • 2008-05-01
    • US11928720
    • 2007-10-30
    • Joon Hyung LIMTah Joon ParkKwang Mook LeeKoon Shik Cho
    • Joon Hyung LIMTah Joon ParkKwang Mook LeeKoon Shik Cho
    • H03K3/02
    • H03K3/011H03L7/06
    • There is provided an RC oscillation circuit capable of adjusting an oscillation frequency, and an oscillation method thereof. The RC oscillation circuit including: an RC oscillator including a variable resistor and a variable capacitor, the RC oscillator generating an RC oscillating signal having a frequency determined by a resistance of the variable resistor and a capacitance of the variable capacitor; a counter counting a clock number of a reference oscillating signal corresponding to one period of the RC oscillating signal to generate a first count value, the reference oscillating signal having a preset frequency; and a frequency controller controlling a frequency of the RC oscillating signal by determining the resistance of the variable resistor and the capacitance of the variable capacitor such that a difference between the first count value and a preset second count value is smaller than a preset first critical value.
    • 提供了能够调节振荡频率的RC振荡电路及其振荡方法。 RC振荡电路包括:包括可变电阻器和可变电容器的RC振荡器,RC振荡器产生具有由可变电阻器的电阻和可变电容器的电容确定的频率的RC振荡信号; 计数对应于RC振荡信号的一个周期的参考振荡信号的时钟数,以产生第一计数值,所述参考振荡信号具有预置频率; 以及频率控制器,通过确定可变电阻器的电阻和可变电容器的电容来控制RC振荡信号的频率,使得第一计数值和预设的第二计数值之间的差小于预设的第一临界值 。
    • 2. 发明授权
    • Resistor-capacitor oscillation circuit capable of adjusting oscillation frequency and method of the same
    • 电阻电容振荡电路能够调节振荡频率及其方法
    • US07612624B2
    • 2009-11-03
    • US11928720
    • 2007-10-30
    • Joon Hyung LimTah Joon ParkKwang Mook LeeKoon Shik Cho
    • Joon Hyung LimTah Joon ParkKwang Mook LeeKoon Shik Cho
    • H03K3/02
    • H03K3/011H03L7/06
    • An RC oscillation circuit and method capable of adjusting an oscillation frequency includes: an RC oscillator including a variable resistor and a variable capacitor, the RC oscillator generating an RC oscillating signal having a frequency determined by a resistance of the variable resistor and a capacitance of the variable capacitor; a counter counting a clock number of a reference oscillating signal corresponding to one period of the RC oscillating signal to generate a first count value, the reference oscillating signal having a preset frequency; and a frequency controller controlling a frequency of the RC oscillating signal by determining the resistance of the variable resistor and the capacitance of the variable capacitor such that a difference between the first count value and a preset second count value is smaller than a preset first critical value.
    • 一种能够调节振荡频率的RC振荡电路和方法包括:RC振荡器,包括可变电阻器和可变电容器,RC振荡器产生具有由可变电阻器的电阻确定的频率的RC振荡信号和 可变电容器 计数对应于RC振荡信号的一个周期的参考振荡信号的时钟数,以产生第一计数值,所述参考振荡信号具有预置频率; 以及频率控制器,通过确定可变电阻器的电阻和可变电容器的电容来控制RC振荡信号的频率,使得第一计数值和预设的第二计数值之间的差小于预设的第一临界值 。
    • 8. 发明申请
    • SLEEP CURRENT ADJUSTING CIRCUIT OF SYSTEM ON CHIP
    • 休眠电流调节系统芯片电路
    • US20080278139A1
    • 2008-11-13
    • US12105966
    • 2008-04-18
    • Yong Il KwonMyeung Su KimJoon Hyung LimKoon Shik ChoTah Joon Park
    • Yong Il KwonMyeung Su KimJoon Hyung LimKoon Shik ChoTah Joon Park
    • H02M3/156
    • G11C5/14G11C5/148
    • There is provided a sleep current adjusting circuit of a system on chip including: a regulator supplying a turn-on voltage and a normal current when a mode selection signal is a normal mode signal, and a turn-off voltage when the mode selection signal is a sleep mode signal; a switching device turned on by the turn-on voltage of the regulator to supply the normal current from the regulator to a main circuit part and a sleep operation circuit part, respectively, and turned off by the turn-off voltage of the regulator to block the normal current from being supplied to the main circuit part and supply the sleep current to the sleep operation circuit part; and a current limit device limiting an operating current flowing in response to the operating voltage and supplying the sleep current to the sleep operation circuit part.
    • 提供了一种片上系统的睡眠电流调节电路,包括:当模式选择信号是正常模式信号时,提供接通电压和正常电流的调节器,以及当模式选择信号为 睡眠模式信号; 开关装置由调节器的导通电压导通,以分别将调节器的正常电流提供给主电路部分和睡眠操作电路部分,并通过调节器的截止电压将其截止以阻止 正常电流被提供给主电路部分并将睡眠电流提供给睡眠操作电路部分; 以及电流限制装置,其限制响应于所述工作电压流动的工作电流并将睡眠电流提供给所述睡眠操作电路部分。
    • 10. 发明申请
    • DUAL MODE WPAN TRANSCEIVER
    • 双模WPAN收发器
    • US20080137570A1
    • 2008-06-12
    • US11951040
    • 2007-12-05
    • Sang Hyun MINTah Joon ParkKoon Shik ChoJae Hyung Lee
    • Sang Hyun MINTah Joon ParkKoon Shik ChoJae Hyung Lee
    • H04B7/00H04L27/00
    • H04L27/3872H04B1/005H04B1/707H04B1/7163H04B1/71635H04B1/71637H04B2201/70705
    • There is provided a dual mode WPAN transceiver including a dual mode WPAN transmitter and a dual mode WPAN receiver. In the dual mode WPAN transceiver, the dual mode WPAN transmitter includes a low-speed spreading transmission block spreading low bit-rate data corresponding to a low data rate in low data rate mode, and a high-speed encoding transmission block encoding high bit-rate data corresponding to a high data rate in high data rate mode, and the dual mode WPAN receiver includes an A/D block converting analog I and Q signals into digital I and Q signals, a differential block obtaining a phase difference between the digital I and Q signals from the A/D unit and complex signals adjacent thereto to offset phase errors of the digital I and Q signals, a low-speed despreading reception unit despreading the digital I and Q signals differentiated by the differential block to detect low bit-rate data in low data rate mode, and a high-speed decoding reception unit decoding the digital I and Q signals differentiated by the differential block to detect high bit-rate data.
    • 提供了一种双模WPAN收发器,包括双模WPAN发送器和双模WPAN接收器。 在双模WPAN收发器中,双模WPAN发送器包括一个低速扩展传输块,它以低数据速率模式扩展对应于低数据速率的低比特率数据,以及一个高位编码传输块, 速率数据对应于高数据速率模式下的高数据速率,双模WPAN接收机包括将模拟I和Q信号转换成数字I和Q信号的A / D块,差分块获得数字I 和来自A / D单元的Q信号和与其相邻的复信号以消除数字I和Q信号的相位误差;低速解扩接收单元解扩由差分块区分的数字I和Q信号,以检测低位 - 低数据速率模式的速率数据,以及对由差分块区分的数字I和Q信号进行解码以检测高比特率数据的高速解码接收单元。