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    • 5. 发明授权
    • Recessed transistor and method of manufacturing the same
    • 嵌入式晶体管及其制造方法
    • US09012982B2
    • 2015-04-21
    • US12068179
    • 2008-02-04
    • Keun-Nam KimMakoto YoshidaChul LeeDong-Gun ParkWoun-Suck Yang
    • Keun-Nam KimMakoto YoshidaChul LeeDong-Gun ParkWoun-Suck Yang
    • H01L29/66H01L29/78
    • H01L29/66795H01L29/66621H01L29/7834H01L29/7851
    • A recessed transistor and a method of manufacturing the same are provided. The recessed transistor may include a substrate, an active pin, a gate pattern and source and drain regions. The substrate may include an isolation layer that establishes an active region and a field region of the substrate. The substrate may include a recessed structure having an upper recess formed in the active region and a lower recess in communication with the upper recess. An active pin may be formed in a region between side surfaces of the isolation layer and the lower recess and an interface between the active region and the field region. The gate pattern may include a gate insulation layer formed on an inner surface of the recessed structure and a gate electrode formed on the gate insulation layer in the recessed structure. The source/drain regions may be formed adjacent to the active region and the gate electrode.
    • 提供凹陷晶体管及其制造方法。 凹陷的晶体管可以包括衬底,有源引脚,栅极图案以及源极和漏极区域。 衬底可以包括建立衬底的有源区和场区的隔离层。 衬底可以包括具有形成在有源区域中的上凹部的凹陷结构和与上凹部连通的下凹部。 有源销可以形成在隔离层和下凹部的侧表面之间的区域中以及有源区域和场区域之间的界面。 栅极图案可以包括形成在凹陷结构的内表面上的栅极绝缘层和形成在凹陷结构中的栅极绝缘层上的栅电极。 源/漏区可以与有源区和栅电极相邻形成。
    • 10. 发明申请
    • Semiconductor Devices Including Transistors Having Three Dimensional Channels
    • 包括具有三维通道的晶体管的半导体器件
    • US20080315282A1
    • 2008-12-25
    • US12199237
    • 2008-08-27
    • Eun-Suk ChoChul Lee
    • Eun-Suk ChoChul Lee
    • H01L29/788
    • H01L23/485H01L29/41791H01L29/66795H01L29/785H01L29/7853H01L29/7854H01L2029/7858H01L2924/0002H01L2924/00
    • Semiconductor devices including a gate electrode crossing over a semiconductor fin on a semiconductor substrate are provided. A gate insulating layer is provided between the gate electrode and the semiconductor fin. A channel region having a three-dimensional structure defined at the semiconductor fin under the gate electrode is also provided. Doped region is provided in the semiconductor fin at either side of the gate electrode and an interlayer insulating layer is provided on a surface of the semiconductor substrate. A connector region is coupled to the doped region and provided in an opening, which penetrates the interlayer insulating layer. A recess region is provided in the doped region and is coupled to the connector region. The connector region contacts an inner surface of the recess region. Related methods of fabricating semiconductor devices are also provided herein.
    • 提供包括在半导体衬底上与半导体鳍状物交叉的栅电极的半导体器件。 栅极绝缘层设置在栅电极和半导体鳍之间。 还提供了在栅电极下方的半导体鳍片处限定的具有三维结构的沟道区域。 掺杂区域设置在栅电极的任一侧的半导体鳍片中,并且在半导体衬底的表面上设置层间绝缘层。 连接器区域耦合到掺杂区域并且设置在穿过层间绝缘层的开口中。 在掺杂区域中提供凹陷区域并且耦合到连接器区域。 连接器区域接触凹部区域的内表面。 本文还提供了制造半导体器件的相关方法。