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    • 1. 发明授权
    • Apparatus and method for detecting signal in a spatial multiplexing multiple input multiple output communication system
    • 一种空间复用多输入多输出通信系统中的信号检测装置及方法
    • US08681901B2
    • 2014-03-25
    • US13016325
    • 2011-01-28
    • Joo-Yeol YangJae-Seok KimIn-Hyoung KimYun-Ho JungHae-Dong YeonKil-Hwan KimMi-Suk Cho
    • Joo-Yeol YangJae-Seok KimIn-Hyoung KimYun-Ho JungHae-Dong YeonKil-Hwan KimMi-Suk Cho
    • H04L27/06H04L27/00
    • H04L27/06
    • A Spatial Multiplexing Multiple Input Multiple Output (SM-MIMO) communication system, which generates Q and R matrices through QR decomposing a channel matrix in an array order corresponding to an order of transmission antennas of a signal transmission device, determines a detection order of transmission symbols included in a transmission symbol vector, QR decomposes a reception signal vector and generates the QR decomposed reception signal vector as a transformed reception signal vector, substitutes all of transmittable candidate symbols for a transmission symbol corresponding to a first detection order among the transmission symbols and sequentially removes interference in the transformed reception signal vector, detects candidate symbols of transmission symbols corresponding to a remaining detection order from the interference-removed transformed reception signal vector, combines the detected candidate symbols, detects candidate symbol vectors, and calculates Log-Likelihood Ratio values of bits included in the transmission symbols by using the detected vectors.
    • 空间多路复用多输入多输出(SM-MIMO)通信系统通过QR分解与信号传输装置的发送天线的顺序相对应的阵列顺序的信道矩阵来生成Q和R矩阵,确定传输的检测顺序 包含在发送符号向量中的符号,QR分解接收信号矢量并生成QR分解接收信号矢量作为变换的接收信号矢量,将发送候选符号的全部替换为与发送符号中的第一检测顺序对应的发送符号, 依次去除变换的接收信号矢量中的干扰,从干扰去除的变换的接收信号矢量中检测与剩余检测顺序对应的发送符号的候选符号,合并检测到的候选符号,检测候选符号向量,并计算对数似然比va 通过使用检测到的矢量,包含在发送符号中的比特数。
    • 2. 发明申请
    • APPARATUS AND METHOD FOR DETECTING SIGNAL IN A SPATIAL MULTIPLEXING MULTIPLE INPUT MULTIPLE OUTPUT COMMUNICATION SYSTEM
    • 用于在空间多路复用多输入多输出通信系统中检测信号的装置和方法
    • US20110188615A1
    • 2011-08-04
    • US13016325
    • 2011-01-28
    • Joo-Yeol YangJae-Seok KimIn-Hyoung KimYun-Ho JungHae-Dong YeonKil-Hwan KimMi-Suk Cho
    • Joo-Yeol YangJae-Seok KimIn-Hyoung KimYun-Ho JungHae-Dong YeonKil-Hwan KimMi-Suk Cho
    • H04L27/06
    • H04L27/06
    • A Spatial Multiplexing Multiple Input Multiple Output (SM-MIMO) communication system, which generates a Q matrix and an R matrix through QR decomposing a channel matrix in an array order corresponding to an order of transmission antennas of a signal transmission device, determines a detection order of transmission symbols included in a transmission symbol vector, QR decomposes a reception signal vector and generates the QR decomposed reception signal vector as a transformed reception signal vector, substitutes all of transmittable candidate symbols for a transmission symbol corresponding to a first detection order among the transmission symbols and sequentially removes interference in the transformed reception signal vector, detects candidate symbols of transmission symbols corresponding to a remaining detection order from the interference-removed transformed reception signal vector, combines the detected candidate symbols, detects candidate symbol vectors, and calculates Log-Likelihood Ratio values of bits included in the transmission symbols by using the detected vectors.
    • 空间多路复用多输入多输出(SM-MIMO)通信系统通过以与信号传输设备的发送天线的顺序对应的阵列顺序分解信道矩阵的QR来生成Q矩阵和R矩阵来确定检测 包含在发送符号矢量中的发送符号的顺序,QR分解接收信号矢量,并生成QR分解接收信号矢量作为变换后的接收信号矢量,将所有可发送候选符号代入与第一检测顺序对应的发送符号 传输符号并且顺序地去除经变换的接收信号矢量中的干扰,从干扰去除的变换的接收信号向量中检测与剩余检测顺序对应的传输符号的候选符号,组合检测到的候选符号,检测候选符号向量, Likelihoo d通过使用所检测的向量,包括在发送符号中的比特比率值。
    • 6. 发明授权
    • Methods of manufacturing a semiconductor device
    • 制造半导体器件的方法
    • US08470663B2
    • 2013-06-25
    • US13048683
    • 2011-03-15
    • Seong-Kyu YunJae-Seok Kim
    • Seong-Kyu YunJae-Seok Kim
    • H01L21/8238
    • H01L21/823807H01L21/31053H01L21/823814H01L21/823828H01L23/544H01L29/7848H01L2223/54426H01L2223/54453H01L2924/0002H01L2924/00
    • Methods of manufacturing a semiconductor device include forming integrated structures of polysilicon patterns and hard mask patterns on a substrate divided into at least an NMOS forming region and a PMOS forming region. A first preliminary insulating interlayer is formed on the integrated structures. A first polishing of the first preliminary insulating interlayer is performed until at least one upper surface of the hard mask patterns is exposed, to form a second preliminary insulating interlayer. The second preliminary insulating interlayer is etched until the upper surfaces of the hard mask patterns are exposed, to form a third preliminary insulating interlayer. A second polishing of the hard mask patterns and the third preliminary insulating interlayer is performed until the polysilicon patterns are exposed to form an insulating interlayer. The polysilicon patterns are removed to form an opening. A metal material is deposed to form a gate electrode pattern in the opening.
    • 制造半导体器件的方法包括在分成至少NMOS形成区域和PMOS形成区域的衬底上形成多晶硅图案和硬掩模图案的集成结构。 在集成结构上形成第一初步绝缘中间层。 执行第一初步绝缘中间层的第一次抛光,直到暴露硬掩模图案的至少一个上表面,以形成第二预绝缘中间层。 蚀刻第二初步绝缘中间层直到硬掩模图案的上表面露出,以形成第三初步绝缘中间层。 执行硬掩模图案和第三预备绝缘中间层的第二次抛光,直到多晶硅图案暴露以形成绝缘中间层。 去除多晶硅图形以形成开口。 金属材料被放弃以在开口中形成栅极电极图案。
    • 8. 发明授权
    • Methods of manufacturing a semiconductor device
    • 制造半导体器件的方法
    • US08399327B2
    • 2013-03-19
    • US13240560
    • 2011-09-22
    • Jong-Won LeeJae-Seok KimBo-Un Yoon
    • Jong-Won LeeJae-Seok KimBo-Un Yoon
    • H01L21/336
    • H01L21/823842H01L21/823437H01L29/165H01L29/66545H01L29/66628H01L29/7835
    • A method includes forming a plurality of dummy gate structures on a substrate, each dummy gate structure including a dummy gate electrode and a dummy gate mask, forming a first insulation layer on the substrate and the dummy gate structures to fill a first space between the dummy gate structures, planarizing upper portions of the first insulation layer and the dummy gate structures, removing the remaining first insulation layer to expose a portion of the substrate, forming an etch stop layer on the remaining dummy gate structures and the exposed portion of the substrate, forming a second insulation layer on the etch stop layer to fill a second space between the dummy gate structures, planarizing upper portions of the second insulation layer and the etch stop layer to expose the dummy gate electrodes, removing the exposed dummy gate electrodes to form trenches, and forming metal gate electrodes in the trenches.
    • 一种方法包括在衬底上形成多个虚拟栅极结构,每个虚拟栅极结构包括伪栅极电极和伪栅极掩模,在衬底上形成第一绝缘层和虚拟栅极结构以填充虚拟栅极结构之间的第一空间 栅极结构,平坦化第一绝缘层和伪栅极结构的上部,去除剩余的第一绝缘层以暴露衬底的一部分,在剩余的虚设栅极结构和衬底的暴露部分上形成蚀刻停止层, 在所述蚀刻停止层上形成第二绝缘层以填充所述虚拟栅极结构之间的第二空间,平坦化所述第二绝缘层的上部和所述蚀刻停止层以暴露所述伪栅电极,去除所述暴露的伪栅电极以形成沟槽 并且在沟槽中形成金属栅电极。
    • 9. 发明申请
    • METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE
    • 制造半导体器件的方法
    • US20120122283A1
    • 2012-05-17
    • US13240560
    • 2011-09-22
    • Jong-Won LEEJae-Seok KimBo-Un Yoon
    • Jong-Won LEEJae-Seok KimBo-Un Yoon
    • H01L21/336H01L21/28
    • H01L21/823842H01L21/823437H01L29/165H01L29/66545H01L29/66628H01L29/7835
    • A method includes forming a plurality of dummy gate structures on a substrate, each dummy gate structure including a dummy gate electrode and a dummy gate mask, forming a first insulation layer on the substrate and the dummy gate structures to fill a first space between the dummy gate structures, planarizing upper portions of the first insulation layer and the dummy gate structures, removing the remaining first insulation layer to expose a portion of the substrate, forming an etch stop layer on the remaining dummy gate structures and the exposed portion of the substrate, forming a second insulation layer on the etch stop layer to fill a second space between the dummy gate structures, planarizing upper portions of the second insulation layer and the etch stop layer to expose the dummy gate electrodes, removing the exposed dummy gate electrodes to form trenches, and forming metal gate electrodes in the trenches.
    • 一种方法包括在衬底上形成多个虚拟栅极结构,每个虚拟栅极结构包括伪栅极电极和伪栅极掩模,在衬底上形成第一绝缘层和虚拟栅极结构以填充虚拟栅极结构之间的第一空间 栅极结构,平坦化第一绝缘层和伪栅极结构的上部,去除剩余的第一绝缘层以暴露衬底的一部分,在剩余的虚设栅极结构和衬底的暴露部分上形成蚀刻停止层, 在所述蚀刻停止层上形成第二绝缘层以填充所述虚拟栅极结构之间的第二空间,平坦化所述第二绝缘层的上部和所述蚀刻停止层以暴露所述伪栅电极,去除所述暴露的伪栅电极以形成沟槽 并且在沟槽中形成金属栅电极。
    • 10. 发明授权
    • Branch metric module in viterbi decoder
    • 维特比解码器中的分支度量模块
    • US5727029A
    • 1998-03-10
    • US575076
    • 1995-12-19
    • In-San JeonIk-Su EoIn-Ki LimKwang-Il YeonJae-Seok Kim
    • In-San JeonIk-Su EoIn-Ki LimKwang-Il YeonJae-Seok Kim
    • H03M13/00H03M13/41H04L1/00H03D1/00H04L27/06
    • H03M13/3961H03M13/4107H04L1/0054
    • The present invention relates in general to a channel CODEC to increase the transmitting effect on a communication channel of a communication system, and more specifically to a branch metric module of a viterbi decoder. The module includes an operator for operating and outputting the differential magnitude of two signals, one signal being a code word generated to perform the viterbi decode and the other being a signal transmitted through the channel. An adder sums and outputs the data which is outputted to it from the operator. A receiving code word converter converts the magnitude of any of bits by the linear sampling quantization process, and non-linearly converts it in accordance with a preestimated or predetermined format. A number of operators calculate the magnitude between two signals at the absolute value to convert the magnitude of an inputted generative code word and the magnitude of the non-linear converted receiving code word. The adder sums and outputs the result to a branch metric converter, which converts the output according to the preestimated format.
    • 本发明一般涉及增加对通信系统的通信信道的传输效果的信道CODEC,更具体地涉及维特比解码器的分支量度模块。 该模块包括用于操作和输出两个信号的差分幅度的操作器,一个信号是被执行维特比解码而产生的代码字,另一个是通过该信道发送的信号。 加法器对从操作者向其输出的数据进行求和并输出。 接收码字转换器通过线性采样量化处理来转换任何位的幅度,并且根据预先预定的格式非线性地转换它。 许多算子以绝对值计算两个信号之间的幅度,以转换输入的生成码字的大小和非线性转换的接收码字的大小。 加法器将结果相加并输出到分支度量转换器,该转换器根据预先预定的格式转换输出。