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1. 发明申请

US20060265565A1 Dual edge command 有权
公开(公告)号：US20060265565A1
公开(公告)日：2006-11-23
申请号：US11495418
申请日：2006-07-28
申请人： Joo Choi , Troy Manning , Brent Keeth
发明人： Joo Choi , Troy Manning , Brent Keeth
IPC分类号： G06F13/00
CPC分类号： G11C11/4076 , G06F12/0207 , G06F13/1668 , G11C7/1072 , G11C7/1078 , G11C7/109 , G11C11/408 , G11C11/409
摘要： A technique to increase transfer rate of command and address signals via a given number of command and address pins in each of one or more integrated circuit memory devices during a clock cycle of a clock signal. In one example embodiment, the command and address signals are sent on both rising and falling edges of a clock cycle of a clock signal to increase the transfer rate and essentially reduce the number of required command and address pins in each integrated circuit memory device.

2. 发明申请

US20060045206A1 Method and system for generating reference voltages for signal receivers 有权
公开(公告)号：US20060045206A1
公开(公告)日：2006-03-02
申请号：US10930543
申请日：2004-08-30
申请人： Brent Keeth , Joo Choi , George Pax , Ronnie Harrison , David Ovard , Dragos Dimitriu , Troy Manning , Roy Greeff , Greg King , Brian Johnson
发明人： Brent Keeth , Joo Choi , George Pax , Ronnie Harrison , David Ovard , Dragos Dimitriu , Troy Manning , Roy Greeff , Greg King , Brian Johnson
IPC分类号： H04L27/06
CPC分类号： H04L25/062
摘要： A method and system for generating a reference voltage for memory device signal receivers operates in either a calibration mode or a normal operating mode. In the calibration mode, the magnitude of the reference voltage is incrementally varied, and a digital signal pattern is coupled to the receiver at each reference voltage. An output of the receiver is analyzed to determine if the receiver can accurately pass the signal pattern at each reference voltage level. A range of reference voltages that allow the receiver to accurately pass the signal pattern is recorded, and a final reference voltage is calculated at the approximate midpoint of the range. This final reference voltage is applied to the receiver during normal operation.

3. 发明申请

US20060203938A1 Method and system for generating reference voltages for signal receivers 有权
公开(公告)号：US20060203938A1
公开(公告)日：2006-09-14
申请号：US11433322
申请日：2006-05-11
申请人： Brent Keeth , Joo Choi , George Pax , Ronnie Harrison , David Ovard , Dragos Dimitriu , Troy Manning , Roy Greeff , Greg King , Brian Johnson
发明人： Brent Keeth , Joo Choi , George Pax , Ronnie Harrison , David Ovard , Dragos Dimitriu , Troy Manning , Roy Greeff , Greg King , Brian Johnson
IPC分类号： H04L25/06
CPC分类号： H04L25/062
摘要： A method and system for generating a reference voltage for memory device signal receivers operates in either a calibration mode or a normal operating mode. In the calibration mode, the magnitude of the reference voltage is incrementally varied, and a digital signal pattern is coupled to the receiver at each reference voltage. An output of the receiver is analyzed to determine if the receiver can accurately pass the signal pattern at each reference voltage level. A range of reference voltages that allow the receiver to accurately pass the signal pattern is recorded, and a final reference voltage is calculated at the approximate midpoint of the range. This final reference voltage is applied to the receiver during normal operation.

4. 发明申请

US20050172095A1 Dual edge command in DRAM 有权
标题翻译： DRAM中的双边沿命令
公开(公告)号：US20050172095A1
公开(公告)日：2005-08-04
申请号：US10767555
申请日：2004-01-29
申请人： Joo Choi , Troy Manning , Brent Keeth
发明人： Joo Choi , Troy Manning , Brent Keeth
IPC分类号： G06F12/00 , G11C7/10
CPC分类号： G11C11/4076 , G06F12/0207 , G06F13/1668 , G11C7/1072 , G11C7/1078 , G11C7/109 , G11C11/408 , G11C11/409
摘要： A technique to increase transfer rate of command and address signals via a given number of command and address pins in each of one or more integrated circuit memory devices during a clock cycle of a clock signal. In one example embodiment, the command and address signals are sent on both rising and falling edges of a clock cycle of a clock signal to increase the transfer rate and essentially reduce the number of required command and address pins in each integrated circuit memory device.
摘要翻译：一种在时钟信号的时钟周期期间通过给定数量的一个或多个集成电路存储器件中的每一个中的命令和地址引脚来增加命令和寻址信号的传送速率的技术。在一个示例实施例中，命令和地址信号在时钟信号的时钟周期的上升沿和下降沿上发送，以增加传输速率，并且基本上减少每个集成电路存储器件中所需的命令和地址引脚的数量。

5. 发明申请

US20050165999A1 Memory device having strobe terminals with multiple functions 失效
标题翻译：具有多个功能的选通端子的存储器件
公开(公告)号：US20050165999A1
公开(公告)日：2005-07-28
申请号：US10765310
申请日：2004-01-27
申请人： Joo Choi , Troy Manning
发明人： Joo Choi , Troy Manning
IPC分类号： G11C7/10 , G11C7/22 , G06F12/00
CPC分类号： G11C7/1078 , G11C7/1051 , G11C7/1063 , G11C7/1066 , G11C7/1072 , G11C7/109 , G11C7/1093 , G11C2207/2254
摘要： A memory device has data transceivers, write strobe transceivers, and read strobe transceivers. The data transceivers transfer input data to the memory device and transfer output data from the memory device. The write strobe transceivers transfer timing information of the input data. The read strobe transceivers transfer timing information of the output data. The memory device also has an auxiliary circuit for generating auxiliary information. The auxiliary information includes information different from the timing information of the input data and the output data. The auxiliary circuit uses the write and read transceivers to transfer the auxiliary information to and from the memory device.
摘要翻译：存储器件具有数据收发器，写选通收发器和读选通收发器。数据收发器将输入数据传输到存储器件并从存储器件传送输出数据。写入选通收发器传送输入数据的定时信息。读选通收发器传输输出数据的定时信息。存储装置还具有用于产生辅助信息的辅助电路。辅助信息包括与输入数据和输出数据的定时信息不同的信息。辅助电路使用写入和读取收发器将辅助信息传送到存储器件和从存储器件传送辅助信息。

6. 发明申请

US20060198229A1 MEMORY DEVICE HAVING TERMINALS FOR TRANSFERRING MULTIPLE TYPES OF DATA 有权
标题翻译：具有用于传输多种数据类型的终端的存储器件
公开(公告)号：US20060198229A1
公开(公告)日：2006-09-07
申请号：US11382641
申请日：2006-05-10
申请人： Joo Choi
发明人： Joo Choi
IPC分类号： G11C8/00
CPC分类号： G11C7/1063 , G06F11/1032 , G11C5/066 , G11C7/04 , G11C7/1006 , G11C7/1048 , G11C7/1075 , G11C11/4096 , G11C29/022 , G11C29/028 , G11C2029/0409 , G11C2207/2254
摘要： Some embodiments of the invention include a memory device having a number of terminals for transferring input data and output data to and from a memory array. The memory device includes an auxiliary circuit for receiving input auxiliary information associated with the input data and for generating output auxiliary information associated with the output data. The input and output auxiliary information include inverting codes, parity codes, temperature information or time delay information. The input and output auxiliary information are transferred to and from the memory device on the same terminals that the input data and the output data are transferred. Other embodiments are described and claims.
摘要翻译：本发明的一些实施例包括具有用于传送输入数据并向存储器阵列输出数据并从存储器阵列输出数据的多个端子的存储器件。存储器件包括辅助电路，用于接收与输入数据相关联的输入辅助信息并产生与输出数据相关联的输出辅助信息。输入和输出辅助信息包括反转码，奇偶校验码，温度信息或时间延迟信息。输入和输出辅助信息在输入数据和输出数据传输的相同终端上传送到存储器件和从存储器件传送。其他实施例被描述和权利要求。

7. 发明申请

US20070011388A1 Dual port memory with asymmetric inputs and outputs, device, system 审中-公开
标题翻译：具有不对称输入和输出的双端口存储器，器件，系统
公开(公告)号：US20070011388A1
公开(公告)日：2007-01-11
申请号：US11519557
申请日：2006-09-12
申请人： Joo Choi
发明人： Joo Choi
IPC分类号： G06F13/40
CPC分类号： G11C7/1048
摘要： An asymmetric memory interface including an asymmetric read data interface having a read bus width configured to transfer data from a memory device to a memory controller. The asymmetric memory interface further includes an asymmetric write data interface having a write bus width configured to transfer data from the memory controller to the memory device with the write bus width being different from the read bus width. A memory system including the asymmetric memory interface, memory controller and memory device is disclosed. The asymmetric nature of inputs and outputs reduces pin count by avoiding symmetric replication of bus widths for inputs and outputs.
摘要翻译：非对称存储器接口，包括具有被配置为将数据从存储器件传送到存储器控制器的读总线宽度的非对称读数据接口。非对称存储器接口还包括非对称写数据接口，其具有写总线宽度，该写总线宽度被配置为以写总线宽度与读总线宽度不同的方式将数据从存储器控制器传送到存储器件。公开了一种包括非对称存储器接口，存储器控制器和存储器件的存储器系统。输入和输出的不对称性通过避免输入和输出的总线宽度的对称复制来减少引脚数。

8. 发明申请

US20060041704A1 Dual port memory with asymmetric inputs and outputs, device, system and method 有权
标题翻译：具有不对称输入和输出的双端口存储器，器件，系统和方法
公开(公告)号：US20060041704A1
公开(公告)日：2006-02-23
申请号：US10925255
申请日：2004-08-23
申请人： Joo Choi
发明人： Joo Choi
IPC分类号： G11C7/10 , G06F12/14 , G06F13/40
CPC分类号： G11C7/1048
摘要： An asymmetric memory interface including an asymmetric read data interface having a read bus width configured to transfer data from a memory device to a memory controller. The asymmetric memory interface further includes an asymmetric write data interface having a write bus width configured to transfer data from the memory controller to the memory device with the write bus width being different from the read bus width. A memory system including the asymmetric memory interface, memory controller and memory device is disclosed. The asymmetric nature of inputs and outputs reduces pin count by avoiding symmetric replication of bus widths for inputs and outputs. A method of accessing data in a memory device is also disclosed.
摘要翻译：非对称存储器接口，包括具有被配置为将数据从存储器件传送到存储器控制器的读总线宽度的非对称读数据接口。非对称存储器接口还包括非对称写数据接口，其具有写总线宽度，该写总线宽度被配置为以写总线宽度与读总线宽度不同的方式将数据从存储器控制器传送到存储器件。公开了一种包括非对称存储器接口，存储器控制器和存储器件的存储器系统。输入和输出的不对称性通过避免输入和输出的总线宽度的对称复制来减少引脚数。还公开了一种在存储器件中访问数据的方法。

9. 发明申请

US20060039232A1 Read command triggered synchronization circuitry 有权
标题翻译：读命令触发同步电路
公开(公告)号：US20060039232A1
公开(公告)日：2006-02-23
申请号：US10922429
申请日：2004-08-19
申请人： Joo Choi
发明人： Joo Choi
IPC分类号： G11C8/00
CPC分类号： G11C11/4076 , G11C7/1051 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C11/4096
摘要： A memory READ command triggered clock synchronization mode turns on a clock synchronization circuit only for memory READ operations. The clock synchronization circuit achieves a signal lock with the reference clock signal in less time than the column address strobe latency. Precise memory READ operations are thus possible without wasting power when such operations are not performed by allowing the clock synchronization circuitry to be turned off.
摘要翻译：存储器READ命令触发时钟同步模式仅对存储器读操作打开时钟同步电路。时钟同步电路在比列地址选通延迟更短的时间内实现了具有参考时钟信号的信号锁定。因此，当通过允许时钟同步电路被关闭而不执行这种操作时，精确存储器读操作就可能不浪费电力。

10. 发明申请

US20050190622A1 System and method for communicating information to a memory device using a reconfigured device pin 有权
标题翻译：使用重新配置的器件引脚将信息传送到存储器件的系统和方法
公开(公告)号：US20050190622A1
公开(公告)日：2005-09-01
申请号：US10789673
申请日：2004-02-27
申请人： Joo Choi
发明人： Joo Choi
IPC分类号： G06F13/16 , G11C5/06 , G11C7/04 , G11C7/10
CPC分类号： G06F13/1689 , G06F13/1694 , G11C5/066 , G11C7/04 , G11C7/1045 , G11C7/1051 , G11C7/1063
摘要： The present invention is generally directed to communicating information to and from memory devices. In one embodiment, the invention includes a memory system having a memory device having at least one extraneous device pin, a memory controller configured to control the memory device and a signal path extending between the memory device and the controller that includes the at least one extraneous device pin, the signal path being operable to a transfer a selected memory system characteristic between the controller and the memory device.
摘要翻译：本发明一般涉及向存储设备传送信息和从存储设备传送信息。在一个实施例中，本发明包括具有存储器件的存储器系统，存储器件具有至少一个外部器件引脚，存储器控制器被配置为控制存储器件以及在存储器件与控制器之间延伸的信号通路，该信号通路包括至少一个外部设备引脚，所述信号路径可操作以在所述控制器和所述存储器件之间传送选定的存储器系统特性。

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