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1. 发明申请

US20140150103A1 APPLICATION MODULE INJECTION DEVICE, COMPUTING DEVICE INCLUDING APPLICATION MODULE INJECTION FUNCTION, AND RECORDING MEDIUM FOR RECORDING PROGRAM FOR EXECUTING APPLICATION MODULE INJECTION METHOD 有权
标题翻译：应用模块注入装置，包括应用模块注入功能的计算装置和用于执行应用模块注入方法的记录程序的记录介质
公开(公告)号：US20140150103A1
公开(公告)日：2014-05-29
申请号：US13823642
申请日：2010-12-08
申请人： Jong-Young Kim , Jong-II Lee
发明人： Jong-Young Kim , Jong-II Lee
IPC分类号： G06F21/56
CPC分类号： G06F21/56 , G06F9/445 , G06F9/4484
摘要： Provided are an application module injection device, a computing device including an application module injection function, and a recording medium that records a program for executing an application module injection method. The application module injection device includes a function registration unit configured to register, in an operating system (OS), a first callback function for receiving a notice about whether a process corresponding to a program whose execution is instructed by a user is created from the OS and a second callback function for receiving a notice about whether an image corresponding to the program whose execution is instructed by the user is driven, a process information acquisition unit configured to receive the notice about whether the process corresponding to the program whose execution is instructed by the user is created from the OS through the first callback function, a process determination unit configured to select a process generated so as to correspond to the program whose execution is instructed by the user as an application module injection target process when the program whose execution is instructed by the user, which is determined through the second callback function, corresponds to a predetermined type of program, a context change unit configured to change a first entry point included in a context of a thread corresponding to the application module injection target process into a second entry point of an injected application module, and an application module injection unit configured to inject the application module into the application module injection target process.
摘要翻译：提供了应用模块注入装置，包括应用模块注入功能的计算装置和记录用于执行应用模块注入方法的程序的记录介质。应用模块注入装置包括功能注册单元，被配置为在操作系统（OS）中注册第一回调函数，用于接收关于是否从OS创建与用户的指令执行相关的程序的处理的通知以及第二回调功能，用于接收关于与执行由用户指示的程序相对应的图像是否被驱动的通知;处理信息获取单元，被配置为接收关于是否执行指令的程序与所述用户是通过所述第一回调函数从所述OS创建的，所述处理确定单元被配置为当执行为所述执行的程序为所述程序时，选择所生成的处理，以便对应于由用户指示的程序作为应用模块注入目标进程由用户指示，其通过第二回调函数确定响应于预定类型的程序，上下文改变单元，被配置为将包括在与应用模块注入目标进程相对应的线程的上下文中包括的第一入口点改变为注入的应用模块的第二入口点，以及应用模块注入单元被配置为将应用模块注入到应用模块注入目标进程中。

2. 发明授权

US09098701B2 Application module injection device, computing device including application module injection function, and recording medium for recording program for executing application module injection method 有权
标题翻译：应用模块注入装置，包括应用模块注入功能的计算装置和用于执行应用模块注入方法的记录程序的记录介质
公开(公告)号：US09098701B2
公开(公告)日：2015-08-04
申请号：US13823642
申请日：2010-12-08
申请人： Jong-Young Kim , Jong-II Lee
发明人： Jong-Young Kim , Jong-II Lee
IPC分类号： G06F11/00 , G06F12/14 , G06F12/16 , G08B23/00 , G06F21/56 , G06F9/445 , G06F9/44
CPC分类号： G06F21/56 , G06F9/445 , G06F9/4484
摘要： Provided are an application module injection device, a computing device including an application module injection function, and a recording medium that records a program for executing an application module injection method. The application module injection device includes a function registration unit configured to register, in an operating system (OS), a first callback function for receiving a notice about whether a process corresponding to a program whose execution is instructed by a user is created from the OS and a second callback function for receiving a notice about whether an image corresponding to the program whose execution is instructed by the user is driven, a process information acquisition unit configured to receive the notice about whether the process corresponding to the program whose execution is instructed by the user is created from the OS through the first callback function, a process determination unit configured to select a process generated so as to correspond to the program whose execution is instructed by the user as an application module injection target process when the program whose execution is instructed by the user, which is determined through the second callback function, corresponds to a predetermined type of program, a context change unit configured to change a first entry point included in a context of a thread corresponding to the application module injection target process into a second entry point of an injected application module, and an application module injection unit configured to inject the application module into the application module injection target process.
摘要翻译：提供了应用模块注入装置，包括应用模块注入功能的计算装置和记录用于执行应用模块注入方法的程序的记录介质。应用模块注入装置包括功能注册单元，被配置为在操作系统（OS）中注册第一回调函数，用于接收关于是否从OS创建与用户的指令执行相关的程序的处理的通知以及第二回调函数，用于接收关于与执行由用户指示的程序相对应的图像是否被驱动的通知的处理信息获取单元，被配置为接收关于执行指令的程序是否对应于所述用户是通过所述第一回调函数从所述OS创建的，所述处理确定单元被配置为当执行为所述执行的程序为所述程序时，选择所生成的处理，以便对应于由用户指示的程序作为应用模块注入目标进程由用户指示，其通过第二回调函数确定响应于预定类型的程序，上下文改变单元，被配置为将包括在与应用模块注入目标进程相对应的线程的上下文中包括的第一入口点改变为注入的应用模块的第二入口点，以及应用模块注入单元被配置为将应用模块注入到应用模块注入目标进程中。

3. 发明授权

US08982639B2 Nonvolatile memory device and method of driving the same 有权
公开(公告)号：US08982639B2
公开(公告)日：2015-03-17
申请号：US13432149
申请日：2012-03-28
申请人： Jong-Young Kim , Myung-Hoon Choi
发明人： Jong-Young Kim , Myung-Hoon Choi
IPC分类号： G11C11/34 , G11C16/04 , G11C16/24 , H01L27/115
CPC分类号： G11C16/08 , G11C16/0466 , G11C16/0483 , G11C16/24 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L27/11578 , H01L27/11582
摘要： A nonvolatile memory device includes a plurality of memory blocks, and a pass transistor array transmitting a plurality of drive signals to a selected memory block among the plurality of memory blocks in response to a block select signal. The pass transistor array includes high voltage transistors including one common drain and two sources formed in one active region and one of the plurality of drive signals transmitted to the common drain is transmitted to different memory blocks through the two sources.

4. 发明授权

US07682976B2 Methods of forming a phase-change material layer pattern, methods of manufacturing a phase-change memory device and related slurry compositions 有权
标题翻译：形成相变材料层图案的方法，制造相变记忆装置的方法和相关的浆料组合物
公开(公告)号：US07682976B2
公开(公告)日：2010-03-23
申请号：US12292842
申请日：2008-11-26
申请人： Jong-Young Kim
发明人： Jong-Young Kim
IPC分类号： H01L21/302
CPC分类号： H01L27/2409 , H01L27/2436 , H01L45/06 , H01L45/144 , H01L45/1683
摘要： In methods of forming a phase-change material layer pattern, an insulation layer having a recessed portion may be formed on a substrate, and a phase-change material layer may be formed on the insulation layer to fill the recessed portion. A first polishing process may be performed on the phase-change material layer using a first slurry composition to partially remove the phase-change material layer, the first slurry composition having a first polishing selectivity between the insulation layer and the phase-change material layer. A second polishing process may be performed on the phase-change material layer using a second slurry composition to form a phase-change material layer pattern in the recessed portion, the second slurry composition having a second polishing selectivity substantially lower than the first polishing selectivity.
摘要翻译：在形成相变材料层图案的方法中，可以在基板上形成具有凹部的绝缘层，并且可以在绝缘层上形成相变材料层以填充凹部。可以使用第一浆料组合物在相变材料层上进行第一抛光工艺，以部分地除去相变材料层，第一浆料组合物在绝缘层和相变材料层之间具有第一抛光选择性。可以使用第二浆料组合物在相变材料层上进行第二抛光工艺，以在凹部中形成相变材料层图案，第二浆料组合物具有比第一抛光选择性更低的第二抛光选择性。

5. 发明授权

US5901106A Decoder circuit using redundancy signal having a short pulse format 失效
标题翻译：使用具有短脉冲格式的冗余信号的解码器电路
公开(公告)号：US5901106A
公开(公告)日：1999-05-04
申请号：US961049
申请日：1997-10-30
申请人： Min-Chul Chung , Jong-Young Kim
发明人： Min-Chul Chung , Jong-Young Kim
IPC分类号： G11C11/413 , G11C11/401 , G11C29/00 , G11C29/04 , G11C8/00
CPC分类号： G11C29/84
摘要： Disclosed is a decoder circuit including: a redundancy section row decoder for responding a redundancy main word line signal, thereby selecting a redundancy section word line; a normal section row decoder for receiving a redundancy signal and a normal main word line signal applied from a row redundancy address decoder, thereby selecting a section word line; and, a row redundancy address decoder for generating a signal having a pulse width up to before a next cycle following a redundancy cycle as a redundancy signal, thereby providing the signal to the normal section row decoder and providing the redundancy main word line signal to the redundancy section row decoder during the redundancy cycle, in response to a clock transiting in the redundancy cycle.
摘要翻译：公开了一种解码器电路，包括：冗余部分行解码器，用于响应冗余主字线信号，从而选择冗余部分字线; 正常部分行解码器，用于接收从行冗余地址解码器施加的冗余信号和正常主字线信号，从而选择部分字线; 以及行冗余地址解码器，用于产生具有在冗余周期之后的下一个周期之前的脉冲宽度的信号作为冗余信号，从而将信号提供给正常部分行解码器，并将冗余主字线信号提供给冗余周期中的冗余部分行解码器，以响应冗余周期中的时钟转移。

6. 发明授权

US5532620A Input buffer circuit capable of corresponding to variation of operating voltage in semiconductor integrated circuit 失效
标题翻译：输入缓冲电路，能够对应于半导体集成电路中工作电压的变化
公开(公告)号：US5532620A
公开(公告)日：1996-07-02
申请号：US359458
申请日：1994-12-19
申请人： Bo-Sung Seo , Jong-Young Kim
发明人： Bo-Sung Seo , Jong-Young Kim
IPC分类号： G11C11/409 , H03K17/22 , H03K19/003 , H03K19/0175 , H03K19/01
CPC分类号： H03K17/223 , H03K19/00384
摘要： An input buffer circuit for converting a TTL(TTL:Transistor transistor logic) level signal supplied from an outside into an internal CMOS level signal. The input buffer circuit comprises a power voltage terminal supplied with a power voltage, a power voltage sensing signal generator for detecting a level of the power voltage by inputting as source power the power voltage supplied to the power voltage terminal and for outputting a power voltage sensing signal respondent to the detected level, and switching means for convening an external signal into an internal signal and for performing an switching operation in response to a level of the power voltage sensing signal positioned on an output path to output the convened signal.
摘要翻译：一种用于将从外部提供的TTL（TTL：晶体管晶体管逻辑）电平信号转换成内部CMOS电平信号的输入缓冲电路。输入缓冲电路包括供电电源的电源电压端子，电源电压检测信号发生器，用于通过输入电源电压的电源电压作为源电源输入电源电压检测电压检测电平，响应于检测电平的信号;以及用于将外部信号转换成内部信号并响应于位于输出路径上的电力电压感测信号的电平进行开关操作以输出所接收的信号的开关装置。

7. 发明申请

US20090149006A1 Methods of forming a phase-change material layer pattern, methods of manufacturing a phase-change memory device and related slurry compositions 有权
标题翻译：形成相变材料层图案的方法，制造相变记忆装置的方法和相关的浆料组合物
公开(公告)号：US20090149006A1
公开(公告)日：2009-06-11
申请号：US12292842
申请日：2008-11-26
申请人： Jong-Young Kim
发明人： Jong-Young Kim
IPC分类号： H01L21/20
CPC分类号： H01L27/2409 , H01L27/2436 , H01L45/06 , H01L45/144 , H01L45/1683
摘要： In methods of forming a phase-change material layer pattern, an insulation layer having a recessed portion may be formed on a substrate, and a phase-change material layer may be formed on the insulation layer to fill the recessed portion. A first polishing process may be performed on the phase-change material layer using a first slurry composition to partially remove the phase-change material layer, the first slurry composition having a first polishing selectivity between the insulation layer and the phase-change material layer. A second polishing process may be performed on the phase-change material layer using a second slurry composition to form a phase-change material layer pattern in the recessed portion, the second slurry composition having a second polishing selectivity substantially lower than the first polishing selectivity.
摘要翻译：在形成相变材料层图案的方法中，可以在基板上形成具有凹部的绝缘层，并且可以在绝缘层上形成相变材料层以填充凹部。可以使用第一浆料组合物在相变材料层上进行第一抛光工艺，以部分地除去相变材料层，第一浆料组合物在绝缘层和相变材料层之间具有第一抛光选择性。可以使用第二浆料组合物在相变材料层上进行第二抛光工艺，以在凹部中形成相变材料层图案，第二浆料组合物具有比第一抛光选择性更低的第二抛光选择性。

8. 发明授权

US5825698A Redundancy decoding circuit for a semiconductor memory device 失效
标题翻译：用于半导体存储器件的冗余解码电路
公开(公告)号：US5825698A
公开(公告)日：1998-10-20
申请号：US961052
申请日：1997-10-30
申请人： Chang-Rae Kim , Jong-Young Kim , Hee-Choul Park
发明人： Chang-Rae Kim , Jong-Young Kim , Hee-Choul Park
IPC分类号： G11C29/04 , G11C5/14 , G11C11/413 , G11C29/00 , G11C7/00
CPC分类号： G11C29/787 , G11C5/143
摘要： A redundancy decoding circuit for a semiconductor memory device is shown which includes a comparator which decodes and outputs a redundant memory cell address in response to an address signal, where the comparator includes internal fuses that are coupled to an output terminal of the comparator and which can be selectively cut in order to determine the redundant memory cell address. The redundancy decoding circuit also includes a driving unit which supplies a driving current to the output terminal of the comparator in response to a switching control signal. A pulse generator generates a power up pulse having a predetermined width responsive to power up of the redundancy decoding circuit. A switching control signal generator, which includes a master fuse connected in series with a switching element, generates the switching control signal at a predetermined voltage level in response to the power up pulse generated by the pulse generator even when the master fuse is incompletely cut.
摘要翻译：示出了用于半导体存储器件的冗余解码电路，其包括响应于地址信号对冗余存储器单元地址进行解码和输出的比较器，其中比较器包括耦合到比较器的输出端子的内部熔丝，选择性地切割以确定冗余存储单元地址。冗余解码电路还包括驱动单元，其响应于切换控制信号向比较器的输出端提供驱动电流。响应于冗余解码电路的上电，脉冲发生器产生具有预定宽度的上电脉冲。包括与开关元件串联连接的主熔丝的开关控制信号发生器，即使当主熔丝未完全切割时，也响应于由脉冲发生器产生的上电脉冲，以预定电压电平产生开关控制信号。

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