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1. 发明授权

US06887130B2 Chemical mechanical polishing apparatus 有权
标题翻译：化学机械抛光装置
公开(公告)号：US06887130B2
公开(公告)日：2005-05-03
申请号：US10795370
申请日：2004-03-08
申请人： Jong-Won Lee , Chang-Ki Hong , Ho-Young Kim
发明人： Jong-Won Lee , Chang-Ki Hong , Ho-Young Kim
IPC分类号： H01L21/304 , B24B37/26 , B24B41/04 , B24B49/00
CPC分类号： B24B37/26 , B24B41/04
摘要： A chemical mechanical polishing (CMP) apparatus includes a plate that holds a substrate, a pad assembly unit comprising a pad support device, a positioning device, and a rotation device operatively connected to the pad assembly unit. The pad support device comprises a plurality of support plates to which pad pieces of a polishing pad can be attached. The positioning device can move at least one of the plurality of support plates in a direction along a surface of the semiconductor substrate to be polished. Further, the CMP apparatus can control the polishing amount along any portion of a surface of a wafer to be polished.
摘要翻译：化学机械抛光（CMP）装置包括保持基板的板，包括垫支撑装置的垫组件单元，定位装置和可操作地连接到垫组件单元的旋转装置。垫支撑装置包括多个支撑板，抛光垫的垫片可附接到支撑板上。定位装置可以沿着要被抛光的半导体衬底的表面的方向移动多个支撑板中的至少一个。此外，CMP装置可以控制沿抛光晶片的表面的任何部分的抛光量。

2. 发明授权

US07670942B2 Method of fabricating self-aligned contact pad using chemical mechanical polishing process 有权
公开(公告)号：US07670942B2
公开(公告)日：2010-03-02
申请号：US11525490
申请日：2006-09-23
申请人： Ho-Young Kim , Chang-Ki Hong , Bo-Un Yoon , Joon-Sang Park
发明人： Ho-Young Kim , Chang-Ki Hong , Bo-Un Yoon , Joon-Sang Park
IPC分类号： H01L21/4763
CPC分类号： H01L21/76897 , H01L21/7684 , H01L27/10873 , H01L27/10885
摘要： A method of fabricating a self-aligned contact pad (SAC) includes forming stacks of a conductive line and a capping layer on a semiconductor substrate, spacers covering sidewalls of the stacks, and an insulation layer filling gaps between the stacks and exposing the top of the capping layer, etching the capping layer to form damascene grooves, forming a plurality of first etching masks with a material different from that of the capping layer to fill the damascene grooves without covering the top of the insulation layer, and forming a second etching mask having an opening region that exposes some of the first etching masks and a portion of the insulation layer located between the first etching masks. The method further includes etching the portion of the insulation layer exposed by the opening region using the first and second etching masks to form a plurality of opening holes, removing the second etching mask, forming a conductive layer filling the opening holes to cover the remaining first etching masks and performing a chemical mechanical polishing (CMP) process on the conductive layer using the capping layer as a polishing end point to remove the first etching masks such that a plurality of SAC pads separated from each other are formed that fill the opening holes.

3. 发明授权

US06858452B2 Method for isolating self-aligned contact pads 失效
标题翻译：隔离自对准接触垫的方法
公开(公告)号：US06858452B2
公开(公告)日：2005-02-22
申请号：US10688610
申请日：2003-10-17
申请人： Jeong-heon Park , Chang-ki Hong , Jae-dong Lee , Young-rae Park , Ho-Young Kim
发明人： Jeong-heon Park , Chang-ki Hong , Jae-dong Lee , Young-rae Park , Ho-Young Kim
IPC分类号： H01L21/304 , H01L21/321 , H01L21/60 , H01L21/66
CPC分类号： H01L21/76897 , H01L21/3212 , H01L22/00
摘要： A method for isolating SAC pads of a semiconductor device, including determining a chemical mechanical polishing process time necessary to isolate the SAC pads a desired amount by referring to a relationship equation between the extent of isolation of the self-aligned contact pads and the chemical-mechanical polishing process time. The chemical mechanical polishing process is performed for the determined process time on the semiconductor device to isolate the self-aligned contact pads the desired amount. The relationship equation is determined using a test semiconductor device.
摘要翻译：一种用于分离半导体器件的SAC焊盘的方法，包括通过参考自对准接触焊盘的隔离程度与化学机械抛光处理时间之间的关系式来确定将SAC焊盘隔离所需量所需的化学机械抛光处理时间，机械抛光加工时间。对半导体器件上确定的处理时间执行化学机械抛光工艺，以将自对准接触焊盘隔离所需量。使用测试半导体器件确定关系式。

4. 发明申请

US20070184663A1 Method of planarizing a semiconductor device 审中-公开
标题翻译：平面化半导体器件的方法
公开(公告)号：US20070184663A1
公开(公告)日：2007-08-09
申请号：US11702124
申请日：2007-02-05
申请人： Jun-Yong Kim , Ho-Young Kim , Chang-Ki Hong , Bo-Un Yoon , Sung-Ho Shin
发明人： Jun-Yong Kim , Ho-Young Kim , Chang-Ki Hong , Bo-Un Yoon , Sung-Ho Shin
IPC分类号： H01L21/461 , H01L21/302
CPC分类号： H01L21/31053
摘要： Example embodiments are directed to a method of planarizing a semiconductor device. A first CMP process may be performed on an insulating layer to remove a stepped structure of the insulating layer. A second CMP process may be performed to planarize the insulating layer with the stepped structure removed until a given pattern is exposed. A process temperature of the first CMP process may be higher than that of the second CMP process. Accordingly, an initial stepped structure may be more readily removed in a planarization process of a surface of the semiconductor device, which may reduce the CMP process time and may increase the degree of planarization.
摘要翻译：示例性实施例涉及一种平面化半导体器件的方法。可以在绝缘层上执行第一CMP工艺以去除绝缘层的阶梯状结构。可以执行第二CMP工艺以使去除直到给定图案暴露的阶梯结构的绝缘层平坦化。第一CMP工艺的工艺温度可以高于第二CMP工艺的工艺温度。因此，可以在半导体器件的表面的平坦化处理中更容易地去除初始阶梯结构，这可以减少CMP处理时间并且可以增加平坦化程度。

5. 发明授权

US07781281B2 Method of fabricating self-aligned contact pad using chemical mechanical polishing process 有权
标题翻译：使用化学机械抛光工艺制造自对准接触垫的方法
公开(公告)号：US07781281B2
公开(公告)日：2010-08-24
申请号：US12694715
申请日：2010-01-27
申请人： Ho-Young Kim , Chang-Ki Hong , Bo-Un Yoon , Joon-Sang Park
发明人： Ho-Young Kim , Chang-Ki Hong , Bo-Un Yoon , Joon-Sang Park
IPC分类号： H01L21/8238
CPC分类号： H01L21/76897 , H01L21/7684 , H01L27/10873 , H01L27/10885
摘要： A method of fabricating a self-aligned contact pad (SAC) includes forming stacks of a conductive line and a capping layer on a semiconductor substrate, spacers covering sidewalls of the stacks, and an insulation layer filling gaps between the stacks and exposing the top of the capping layer, etching the capping layer to form damascene grooves, forming a plurality of first etching masks with a material different from that of the capping layer to fill the damascene grooves without covering the top of the insulation layer, and forming a second etching mask having an opening region that exposes some of the first etching masks and a portion of the insulation layer located between the first etching masks. The method further includes etching the portion of the insulation layer exposed by the opening region using the first and second etching masks to form a plurality of opening holes, removing the second etching mask, forming a conductive layer filling the opening holes to cover the remaining first etching masks and performing a chemical mechanical polishing (CMP) process on the conductive layer using the capping layer as a polishing end point to remove the first etching masks such that a plurality of SAC pads separated from each other are formed that fill the opening holes.
摘要翻译：一种制造自对准接触焊盘（SAC）的方法包括在半导体衬底上形成导电线和覆盖层的叠层，覆盖堆叠的侧壁的间隔物和填充堆叠之间的间隙的绝缘层，覆盖层，蚀刻覆盖层以形成镶嵌槽，用不同于覆盖层的材料形成多个第一蚀刻掩模以填充镶嵌槽而不覆盖绝缘层的顶部，以及形成第二蚀刻掩模具有暴露一些第一蚀刻掩模的开口区域和位于第一蚀刻掩模之间的绝缘层的一部分。该方法还包括使用第一和第二蚀刻掩模蚀刻由开口区域暴露的绝缘层的部分，以形成多个开孔，去除第二蚀刻掩模，形成填充开孔的导电层以覆盖剩余的第一蚀刻掩模并使用覆盖层作为抛光终点在导电层上进行化学机械抛光（CMP）工艺，以去除第一蚀刻掩模，从而形成填充开孔的彼此分离的多个SAC焊盘。

6. 发明申请

US20070072407A1 Method of fabricating self-aligned contact pad using chemical mechanical polishing process 有权
标题翻译：使用化学机械抛光工艺制造自对准接触垫的方法
公开(公告)号：US20070072407A1
公开(公告)日：2007-03-29
申请号：US11525490
申请日：2006-09-23
申请人： Ho-Young Kim , Chang-Ki Hong , Bo-Un Yoon , Joon-Sang Park
发明人： Ho-Young Kim , Chang-Ki Hong , Bo-Un Yoon , Joon-Sang Park
IPC分类号： H01L21/4763
CPC分类号： H01L21/76897 , H01L21/7684 , H01L27/10873 , H01L27/10885
摘要： A method of fabricating a self-aligned contact pad (SAC) includes forming stacks of a conductive line and a capping layer on a semiconductor substrate, spacers covering sidewalls of the stacks, and an insulation layer filling gaps between the stacks and exposing the top of the capping layer, etching the capping layer to form damascene grooves, forming a plurality of first etching masks with a material different from that of the capping layer to fill the damascene grooves without covering the top of the insulation layer, and forming a second etching mask having an opening region that exposes some of the first etching masks and a portion of the insulation layer located between the first etching masks. The method further includes etching the portion of the insulation layer exposed by the opening region using the first and second etching masks to form a plurality of opening holes, removing the second etching mask, forming a conductive layer filling the opening holes to cover the remaining first etching masks and performing a chemical mechanical polishing (CMP) process on the conductive layer using the capping layer as a polishing end point to remove the first etching masks such that a plurality of SAC pads separated from each other are formed that fill the opening holes.
摘要翻译：一种制造自对准接触焊盘（SAC）的方法包括在半导体衬底上形成导电线和覆盖层的叠层，覆盖堆叠的侧壁的间隔物和填充堆叠之间的间隙的绝缘层，覆盖层，蚀刻覆盖层以形成镶嵌槽，用不同于覆盖层的材料形成多个第一蚀刻掩模以填充镶嵌槽而不覆盖绝缘层的顶部，以及形成第二蚀刻掩模具有暴露一些第一蚀刻掩模的开口区域和位于第一蚀刻掩模之间的绝缘层的一部分。该方法还包括使用第一和第二蚀刻掩模蚀刻由开口区域暴露的绝缘层的部分，以形成多个开孔，去除第二蚀刻掩模，形成填充开孔的导电层以覆盖剩余的第一蚀刻掩模并使用覆盖层作为抛光终点在导电层上进行化学机械抛光（CMP）工艺，以去除第一蚀刻掩模，从而形成填充开孔的彼此分离的多个SAC焊盘。

7. 发明授权

US11726406B2 Method of coating a photoresist and apparatus for performing the same 有权
公开(公告)号：US11726406B2
公开(公告)日：2023-08-15
申请号：US17718648
申请日：2022-04-12
申请人： Sunghwan Kim , Ho-Young Kim , Seok Heo , Dongwook Kim , Sungjin Kim , Chaehung Lim , Jaekyung Park , Jae Hong Lee , Junyoung Lee
发明人： Sunghwan Kim , Ho-Young Kim , Seok Heo , Dongwook Kim , Sungjin Kim , Chaehung Lim , Jaekyung Park , Jae Hong Lee , Junyoung Lee
IPC分类号： G03F7/16 , G03F7/20
CPC分类号： G03F7/162 , G03F7/168 , G03F7/2028
摘要： In a method of coating a photoresist, the photoresist may be provided to an upper surface of a rotating wafer. A hovering solution may be injected to an edge portion of the photoresist under a condition that the hovering solution may be hovered with respect to the edge portion of the photoresist with an air layer being interposed between the hovering solution and the edge portion of the photoresist to limit and/or prevent a bead of the photoresist from being formed on an edge portion of the upper surface of the wafer. Thus, the photoresist having a uniform thickness may be coated on the upper surface of the wafer to improve a yield of a semiconductor device by increasing an effective area of the edge portion of the wafer.

8. 发明授权

US08652910B2 Method for fabricating semiconductor device and device using same 有权
标题翻译：制造半导体器件的方法及其使用方法
公开(公告)号：US08652910B2
公开(公告)日：2014-02-18
申请号：US13438250
申请日：2012-04-03
申请人： Bo-Kyeong Kang , Jae-Seok Kim , Ho-Young Kim , Bo-Un Yoon , Il-Young Yoon
发明人： Bo-Kyeong Kang , Jae-Seok Kim , Ho-Young Kim , Bo-Un Yoon , Il-Young Yoon
IPC分类号： H01L21/336
CPC分类号： H01L21/823431 , H01L21/845
摘要： In a method for fabricating a semiconductor device, a substrate may be provided that includes: a base, an active fin that projects from an upper surface of the base and is integrally formed with the base, and a buffer oxide film pattern formed on the active fin in contact with the active fin. A first dummy gate film may be formed on the substrate to cover the buffer oxide film pattern and the first dummy gate film may be smoothed to expose the buffer oxide film pattern. A second dummy gate film may be formed on the exposed buffer oxide film pattern and the first dummy gate film.
摘要翻译：在制造半导体器件的方法中，可以提供一种基板，其包括：底座，从基座的上表面突出并与基座一体形成的活动翅片，以及形成在活动件上的缓冲氧化膜图案翅片与活动翅片接触。可以在衬底上形成第一伪栅极膜以覆盖缓冲氧化膜图案，并且可以平滑第一伪栅极膜以暴露缓冲氧化膜图案。可以在暴露的缓冲氧化膜图案和第一伪栅极膜上形成第二伪栅极膜。

9. 发明申请

US20110297182A1 METHOD OF MEGASONIC CLEANING OF AN OBJECT 有权
标题翻译：物体清洗方法
公开(公告)号：US20110297182A1
公开(公告)日：2011-12-08
申请号：US12907642
申请日：2010-10-19
申请人： Jae-Hyuck Choi , Won-Jung Kim , Ho-Young Kim , Hyung-Ho Ko , Jong-Keun Oh , Chan-Uk Jeon , Keun-Hwan Park
发明人： Jae-Hyuck Choi , Won-Jung Kim , Ho-Young Kim , Hyung-Ho Ko , Jong-Keun Oh , Chan-Uk Jeon , Keun-Hwan Park
IPC分类号： B08B3/12
CPC分类号： B08B3/12 , G03F1/82 , H01L21/02057 , H01L21/67057
摘要： A megasonic cleaning method and a megasonic cleaning apparatus are provided. Microcavitation bubbles may be formed by applying an electromotive force to a cleaning solution using a megasonic energy in a separate room from an object to be cleaned. The microcavitation bubbles having a stable oscillation among the formed microcavitation bubbles may be moved to the object to be cleaned. A surface of the object to be cleaned may be cleaned using the microcavitation bubbles having the stable oscillation. Particles attached onto the surface of the object to be cleaned may be effectively removed while preventing pattern damage.
摘要翻译：提供了一种兆声波清洗方法和一种超声波清洗装置。微气泡可以通过使用超声波能量在与要清洁的物体分离的房间中的清洁溶液施加电动势来形成。在形成的微气泡之间具有稳定振荡的微气泡可以移动到要清洁的物体。可以使用具有稳定振荡的微气泡来清洁待清洁物体的表面。可以有效地除去附着在待清洁物体表面上的颗粒，同时防止图案损坏。

10. 发明申请

US20100157709A1 Semiconductor memory device having shared temperature control circuit 有权
标题翻译：具有共享温度控制电路的半导体存储器件
公开(公告)号：US20100157709A1
公开(公告)日：2010-06-24
申请号：US12589674
申请日：2009-10-27
申请人： Ho-Young Kim , Jung-Bae Lee
发明人： Ho-Young Kim , Jung-Bae Lee
IPC分类号： G11C7/04 , G11C8/00 , G11C7/00
CPC分类号： G11C29/02 , G11C5/143 , G11C7/04 , G11C11/406 , G11C11/40626 , G11C29/028 , G11C2029/5002 , G11C2207/2254
摘要： A semiconductor memory device includes a plurality of memory banks; a plurality of temperature sensing circuits, and a shared control circuit. The temperature sensing circuits correspond to the memory banks and each is disposed in the vicinity of a corresponding memory bank. The shared control circuit is connected to the plurality of temperature sensing circuits and a plurality of refresh circuits for refreshing the plurality of memory banks, performs calibration on the plurality of temperature sensing circuits, performs digital processing on signals for separately controlling refresh intervals for the plurality of memory banks, and transmits the processed signals to the plurality of refresh circuits. Therefore, the refresh intervals for individual channels or banks are separately or selectively controlled. Further, since the plurality of temperature sensing circuits are connected to the shared temperature control circuit, the occupied area of the circuits in a chip is reduced or minimized.
摘要翻译：半导体存储器件包括多个存储体; 多个温度检测电路和共享控制电路。温度感测电路对应于存储体，并且各自设置在相应的存储体的附近。共享控制电路连接到多个温度检测电路和多个刷新电路，用于刷新多个存储体，对多个温度感测电路进行校准，对用于分别控制多个温度感测电路的刷新间隔的信号执行数字处理的存储体，并且将处理的信号发送到多个刷新电路。因此，单独或选择性地控制各通道或组的刷新间隔。此外，由于多个温度检测电路连接到共享温度控制电路，芯片中的电路的占用面积减小或最小化。

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