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1. 发明授权

US08598012B2 Method for fabricating semiconductor device with buried gates 有权
标题翻译：制造具有埋栅的半导体器件的方法
公开(公告)号：US08598012B2
公开(公告)日：2013-12-03
申请号：US12832137
申请日：2010-07-08
申请人： Jong-Han Shin , Noh-Jung Kwak , Myung-Ok Kim
发明人： Jong-Han Shin , Noh-Jung Kwak , Myung-Ok Kim
IPC分类号： H01L21/76 , H01L21/3205
CPC分类号： H01L21/76229 , H01L21/76897 , H01L27/10876 , H01L27/10894 , H01L29/4236 , H01L29/66621
摘要： A method for fabricating a semiconductor device includes sequentially stacking a pad oxide layer and a hard mask layer over a substrate, forming a device isolation layer over the substrate, forming a capping layer pattern configured to open a first region of the substrate and cover a second region of the substrate, removing the hard mask layer, removing the capping layer pattern, and removing the pad oxide layer.
摘要翻译：一种用于制造半导体器件的方法包括在衬底上顺序堆叠衬垫氧化物层和硬掩模层，在衬底上形成器件隔离层，形成覆盖衬底图案，其构造成打开衬底的第一区域并覆盖第二区域，去除硬掩模层，去除覆盖层图案，以及去除焊盘氧化物层。

2. 发明申请

US20110159664A1 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH BURIED GATES 有权
标题翻译：用于制造具有开口盖的半导体器件的方法
公开(公告)号：US20110159664A1
公开(公告)日：2011-06-30
申请号：US12832137
申请日：2010-07-08
申请人： Jong-Han SHIN , Noh-Jung Kwak , Myung-Ok Kim
发明人： Jong-Han SHIN , Noh-Jung Kwak , Myung-Ok Kim
IPC分类号： H01L21/76 , H01L21/768
CPC分类号： H01L21/76229 , H01L21/76897 , H01L27/10876 , H01L27/10894 , H01L29/4236 , H01L29/66621
摘要： A method for fabricating a semiconductor device includes sequentially stacking a pad oxide layer and a hard mask layer over a substrate, forming a device isolation layer over the substrate, forming a capping layer pattern configured to open a first region of the substrate and cover a second region of the substrate, removing the hard mask layer, removing the capping layer pattern, and removing the pad oxide layer.
摘要翻译：一种用于制造半导体器件的方法包括在衬底上顺序堆叠衬垫氧化物层和硬掩模层，在衬底上形成器件隔离层，形成覆盖衬底图案，其构造成打开衬底的第一区域并覆盖第二区域，去除硬掩模层，去除覆盖层图案，以及去除焊盘氧化物层。

3. 发明授权

US08158529B2 Method for forming active pillar of vertical channel transistor 有权
标题翻译：用于形成垂直沟道晶体管的有源支柱的方法
公开(公告)号：US08158529B2
公开(公告)日：2012-04-17
申请号：US12492559
申请日：2009-06-26
申请人： Myung-Ok Kim
发明人： Myung-Ok Kim
IPC分类号： H01L21/302
CPC分类号： H01L21/30655 , H01L21/3065
摘要： A method for forming an active pillar of a vertical channel transistor includes forming a hard mask pattern on a substrate, etching vertically the substrate using the hard mask pattern as an etch barrier to form an active pillar, and etching horizontally to remove by-product remaining on the exposed substrate, the hard mask pattern and the active pillar and at the same time to reduce line width of the hard mask pattern and the active pillar, wherein a unit cycle in which the vertical etching and the horizontal etching are each performed subsequently once, respectively, is performed repeatedly at least two times or more. According to the present invention, an active pillar having vertical profiles on its sidewalls and having height and line width (or diameter) required in a highly integrated vertical channel transistor can be provided.
摘要翻译：用于形成垂直沟道晶体管的有源柱的方法包括在衬底上形成硬掩模图案，使用硬掩模图案垂直蚀刻衬底作为蚀刻阻挡层以形成有源柱，并水平蚀刻以除去副产物剩余在暴露的基板上，硬掩模图案和有源柱，同时减少硬掩模图案和有源柱的线宽，其中垂直蚀刻和水平蚀刻各自随后进行一次的单位周期分别重复执行至少两次以上。根据本发明，可以提供在其侧壁上具有垂直轮廓并且具有高度集成的垂直通道晶体管中所需的高度和线宽度（或直径）的有源支柱。

4. 发明授权

US07989292B2 Method of fabricating a semiconductor device with a channel formed in a vertical direction 有权
标题翻译：制造具有在垂直方向上形成的通道的半导体器件的方法
公开(公告)号：US07989292B2
公开(公告)日：2011-08-02
申请号：US12334324
申请日：2008-12-12
申请人： Sang-Hoon Cho , Yun-Seok Cho , Myung-Ok Kim , Sang-Hoon Park , Young-Kyun Jung
发明人： Sang-Hoon Cho , Yun-Seok Cho , Myung-Ok Kim , Sang-Hoon Park , Young-Kyun Jung
IPC分类号： H01L21/336
CPC分类号： H01L21/823487 , H01L29/66666
摘要： In a method of fabricating a semiconductor device on a substrate which includes a plurality of pillar patterns, an impurity region between adjacent pillar patterns, a gate electrode on each pillar pattern, a first capping layer covering the gate electrode, and a separation layer covering the first capping layer between the gate electrodes of adjacent pillar patterns, the first capping layer is removed except for a portion contacting the separation layer, a sacrificial layer is formed to cover the gate electrode, a second capping layer is formed on sidewalls of each pillar pattern, the sacrificial layer is removed and a word line connecting the gate electrodes of the adjacent pillar patterns is formed. In the manufactured device, the first capping layer isolates the impurity region from the word line and the second capping region prevents the sidewalls of the respective pillar pattern from being exposed.
摘要翻译：在一种在包括多个柱状图案的基板上制造半导体器件的方法中，相邻柱状图案之间的杂质区域，每个柱状图案上的栅极电极，覆盖栅电极的第一覆盖层和覆盖该栅极电极的分离层在相邻柱状图案的栅电极之间的第一覆盖层除去除了与分离层接触的部分之外的第一覆盖层，形成覆盖栅电极的牺牲层，在每个柱状图案的侧壁上形成第二覆盖层，去除牺牲层，并且形成连接相邻柱状图案的栅电极的字线。在所制造的器件中，第一覆盖层将杂质区域与字线隔离，并且第二封盖区域防止相应柱状图案的侧壁暴露。

5. 发明授权

US07314792B2 Method for fabricating transistor of semiconductor device 有权
标题翻译：制造半导体器件晶体管的方法
公开(公告)号：US07314792B2
公开(公告)日：2008-01-01
申请号：US11321591
申请日：2005-12-30
申请人： Myung-Ok Kim , Tae-Woo Jung , Sung-Kwon Lee , Sea-Ug Jang
发明人： Myung-Ok Kim , Tae-Woo Jung , Sung-Kwon Lee , Sea-Ug Jang
IPC分类号： H01L21/8238 , H01L21/336 , H01L21/331 , H01L21/76
CPC分类号： H01L21/31116 , H01L29/66621
摘要： A method for fabricating a transistor of a semiconductor device is provided. The method includes: forming device isolation layers in a substrate including a bottom structure, thereby defining an active region; etching the active region to a predetermined depth to form a plurality of recess structures each of which has a flat bottom portion with a critical dimension (CD) larger than that of a top portion; and sequentially forming a gate oxide layer and a metal layer on the recess structures; and patterning the gate oxide layer and the metal layer to form a plurality of gate structures.
摘要翻译：提供一种制造半导体器件的晶体管的方法。该方法包括：在包括底部结构的衬底中形成器件隔离层，从而限定有源区; 将活性区域蚀刻到预定深度以形成多个凹部结构，每个凹部结构具有平坦的底部，其临界尺寸（CD）大于顶部部分的临界尺寸; 并且在所述凹部结构上依次形成栅极氧化物层和金属层; 以及图案化栅极氧化物层和金属层以形成多个栅极结构。

6. 发明授权

US07927965B2 Method for fabricating partial SOI substrate 失效
标题翻译：制造部分SOI衬底的方法
公开(公告)号：US07927965B2
公开(公告)日：2011-04-19
申请号：US12492724
申请日：2009-06-26
申请人： Myung-Ok Kim
发明人： Myung-Ok Kim
IPC分类号： H01L21/76
CPC分类号： H01L21/76283 , H01L21/02381 , H01L21/02532 , H01L21/02639 , H01L21/02647 , H01L21/76224 , H01L21/84 , H01L27/10844
摘要： A method for fabricating a partial silicon-on-insulator (SOI) substrate is disclosed. The method for fabricating a partial silicon-on-insulator (SOI) substrate includes forming an insulation pattern over a first silicon layer, forming a second silicon layer over the substrate structure including the insulation pattern, etching the second silicon layer to form trenches, and forming device isolation regions filling the trenches.
摘要翻译：公开了一种用于制造部分绝缘体上硅（SOI）衬底的方法。部分绝缘上绝缘体（SOI）衬底的制造方法包括在第一硅层上形成绝缘图案，在包括绝缘图案的衬底结构之上形成第二硅层，蚀刻第二硅层以形成沟槽，以及形成装置隔离区填充沟槽。

7. 发明申请

US20100055917A1 METHOD FOR FORMING ACTIVE PILLAR OF VERTICAL CHANNEL TRANSISTOR 有权
标题翻译：形成垂直通道晶体管主动支柱的方法
公开(公告)号：US20100055917A1
公开(公告)日：2010-03-04
申请号：US12492559
申请日：2009-06-26
申请人： Myung-Ok Kim
发明人： Myung-Ok Kim
IPC分类号： H01L21/306
CPC分类号： H01L21/30655 , H01L21/3065
摘要： A method for forming an active pillar of a vertical channel transistor includes forming a hard mask pattern on a substrate, etching vertically the substrate using the hard mask pattern as an etch barrier to form an active pillar, and etching horizontally to remove by-product remaining on the exposed substrate, the hard mask pattern and the active pillar and at the same time to reduce line width of the hard mask pattern and the active pillar, wherein a unit cycle in which the vertical etching and the horizontal etching are each performed subsequently once, respectively, is performed repeatedly at least two times or more. According to the present invention, an active pillar having vertical profiles on its sidewalls and having height and line width (or diameter) required in a highly integrated vertical channel transistor can be provided.
摘要翻译：用于形成垂直沟道晶体管的有源柱的方法包括在衬底上形成硬掩模图案，使用硬掩模图案垂直蚀刻衬底作为蚀刻阻挡层以形成有源柱，并水平蚀刻以除去副产物剩余在暴露的基板上，硬掩模图案和有源柱，同时减少硬掩模图案和有源柱的线宽，其中垂直蚀刻和水平蚀刻各自随后进行一次的单位周期分别重复执行至少两次以上。根据本发明，可以提供在其侧壁上具有垂直轮廓并且具有高度集成的垂直通道晶体管中所需的高度和线宽度（或直径）的有源支柱。

8. 发明授权

US07491606B2 Semiconductor device and method for fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07491606B2
公开(公告)日：2009-02-17
申请号：US11360142
申请日：2006-02-22
申请人： Sung-Kwon Lee , Myung-Ok Kim
发明人： Sung-Kwon Lee , Myung-Ok Kim
IPC分类号： H01L21/8242
CPC分类号： H01L29/94 , H01L28/91
摘要： A method for fabricating a three dimensional type capacitor is provided. The method includes forming a first insulation layer including first contact layers over a substrate, forming a second insulation layer over the first insulation layer, forming second contact layers by using a material having an etch selectivity different from the first contact layers such that the second contact layers are connected with the first contact layers within the second insulation layer, forming an etch stop layer over the second insulation layer and the second contact layers, forming a third insulation layer over the etch stop layer, etching the third insulation layer and the etch stop layer to form first contact holes exposing the second contact layers, etching the exposed second contact layers to form second contact holes exposing the first contact holes, and forming bottom electrodes over the inner surface of the second contact holes.
摘要翻译：提供一种制造三维型电容器的方法。该方法包括在衬底上形成包括第一接触层的第一绝缘层，在第一绝缘层上形成第二绝缘层，通过使用具有不同于第一接触层的蚀刻选择性的材料形成第二接触层，使得第二接触层与第二绝缘层内的第一接触层连接，在第二绝缘层和第二接触层上方形成蚀刻停止层，在蚀刻停止层上方形成第三绝缘层，蚀刻第三绝缘层和蚀刻停止层以形成暴露第二接触层的第一接触孔，蚀刻暴露的第二接触层以形成暴露第一接触孔的第二接触孔，以及在第二接触孔的内表面上形成底电极。

9. 发明申请

US20080160774A1 Method for fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20080160774A1
公开(公告)日：2008-07-03
申请号：US12005439
申请日：2007-12-26
申请人： Myung-Ok Kim , Tae-Woo Jung
发明人： Myung-Ok Kim , Tae-Woo Jung
IPC分类号： H01L21/311
CPC分类号： H01L21/32139 , H01L21/31116 , H01L21/3143 , H01L21/3146 , H01L27/105 , H01L27/1052
摘要： A method for fabricating a semiconductor device includes providing a substrate having a first and a second region, forming an etch target layer over the substrate, forming a hard mask layer over the etch target layer to have different thicknesses over the first and the second regions, forming a hard mask pattern by etching the hard mask layer, and etching the etch target layer using the hard mask pattern as an etch mask to form a target pattern having different densities over the first and the second regions.
摘要翻译：一种用于制造半导体器件的方法包括提供具有第一和第二区域的衬底，在衬底上形成蚀刻目标层，在蚀刻目标层上形成硬掩模层，以在第一和第二区域上具有不同的厚度，通过蚀刻硬掩模层形成硬掩模图案，并且使用硬掩模图案作为蚀刻掩模蚀刻蚀刻目标层，以形成在第一和第二区域上具有不同密度的目标图案。

10. 发明授权

US08399324B2 Semiconductor device and method of fabricating the same 有权
公开(公告)号：US08399324B2
公开(公告)日：2013-03-19
申请号：US12318168
申请日：2008-12-23
申请人： Myung-Ok Kim
发明人： Myung-Ok Kim
IPC分类号： H01L21/336
CPC分类号： H01L29/78 , H01L21/31144 , H01L21/32139 , H01L29/66666
摘要： In a method of fabricating a semiconductor device on a substrate having thereon a conductive layer, the conductive layer is patterned to form a plurality of opened regions. A gate insulation layer is formed on a sidewall of each of the opened regions. A pillar pattern is formed in each opened region. On each pillar pattern, a gate electrode, which encloses the pillar pattern, is formed by removing the conductive layer between the pillar patterns.

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