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1. 发明授权

US07129488B2 Surface-normal optical path structure for infrared photodetection 有权
标题翻译：用于红外光电检测的表面法线光路结构
公开(公告)号：US07129488B2
公开(公告)日：2006-10-31
申请号：US10746952
申请日：2003-12-23
申请人： Jong Jan Lee , Jer-Shen Maa , Douglas J. Tweet , Sheng Teng Hsu
发明人： Jong Jan Lee , Jer-Shen Maa , Douglas J. Tweet , Sheng Teng Hsu
IPC分类号： G01J5/20 , G01J5/08
CPC分类号： H01L31/105 , H01L21/02381 , H01L21/0243 , H01L21/0245 , H01L21/02532 , H01L21/02639 , H01L27/14627 , H01L27/14643 , H01L31/02327 , H01L31/028 , H01L31/035281 , H01L31/108 , H01L31/109 , H01L31/1812 , Y02E10/547
摘要： A SiGe surface-normal optical path photodetector structure and a method for forming the SiGe optical path normal structure are provided. The method comprises: forming a Si substrate with a surface; forming a Si feature, normal with respect to the Si substrate surface, such as a via, trench, or pillar; depositing SiGe overlying the Si normal feature to a thickness in the range of 5 to 1000 nanometers (nm); and, forming a SiGe optical path normal structure having an optical path length in the range of 0.1 to 10 microns. Typically, the SiGe has a Ge concentration in the range from 5 to 100%. The Ge concentration may be graded to increase with respect to the deposition thickness. For example, the SiGe may have a 20% concentration of Ge at the Si substrate interface, a 30% concentration of Ge at a SiGe film top surface, and a thickness of 400 nm.
摘要翻译：提供SiGe表面法线光路检测器结构和形成SiGe光路法线结构的方法。该方法包括：用表面形成Si衬底; 形成Si特征，相对于诸如通孔，沟槽或柱的Si衬底表面是正常的; 将Si覆盖Si正常特征的SiGe沉积到5至1000纳米（nm）范围内的厚度; 并且形成光程长度为0.1〜10微米的SiGe光路法线结构。通常，SiGe的Ge浓度为5〜100％。 Ge浓度可以相对于沉积厚度而分级增加。例如，SiGe可以在Si衬底界面处具有20％的Ge浓度，在SiGe膜顶表面上可以具有30％的Ge浓度，并且厚度为400nm。

2. 发明授权

US6140189A Method for fabricating a LOCOS MOS device for ESD protection 有权
标题翻译：用于制造用于ESD保护的LOCOS MOS器件的方法
公开(公告)号：US6140189A
公开(公告)日：2000-10-31
申请号：US248630
申请日：1999-02-11
申请人： Sheng Teng Hsu , Katsumasa Fujii , Hidechika Kawazoe , Jong Jan Lee
发明人： Sheng Teng Hsu , Katsumasa Fujii , Hidechika Kawazoe , Jong Jan Lee
IPC分类号： H01L29/78 , H01L21/8234 , H01L27/02 , H01L27/088 , H01L21/336
CPC分类号： H01L27/0266 , Y10S438/981
摘要： A MOS transistor having a multilevel gate oxide layer is provided for use in an ESD protection circuit. A thick gate oxide layer near the drain insures that the transistor has a relatively large drain to gate breakdown voltage. A thin gate oxide layer near the source permits the gate voltage to turn the transistor on and off with rapid switching speeds. The thick portion of the MOS transistor multilevel gate oxide layer is formed with a local oxidation of silicon (LOCOS) process, while the thin gate layer is formed in a separate step. An ESD protection circuit and method for fabricating the above-mentioned multilevel gate oxide layer MOS transistor are also provided.
摘要翻译：提供具有多电平栅氧化层的MOS晶体管用于ESD保护电路中。在漏极附近的厚栅极氧化层确保晶体管具有相对较大的漏极到栅极击穿电压。靠近源极的薄栅极氧化层允许栅极电压以快速的开关速度开启和关闭晶体管。 MOS晶体管多电平栅极氧化物层的厚部分由硅（LOCOS）工艺的局部氧化形成，而薄栅极层在单独的步骤中形成。还提供了用于制造上述多电平栅极氧化物层MOS晶体管的ESD保护电路和方法。

3. 发明授权

US6018171A Shallow junction ferroelectric memory cell having a laterally extending p-n junction and method of making the same 失效
标题翻译：具有横向延伸的p-n结的浅结铁电存储器单元及其制造方法
公开(公告)号：US6018171A
公开(公告)日：2000-01-25
申请号：US834499
申请日：1997-04-04
申请人： Sheng Teng Hsu , Jong Jan Lee , Chien-Hsiung Peng
发明人： Sheng Teng Hsu , Jong Jan Lee , Chien-Hsiung Peng
IPC分类号： G11C11/22 , H01L21/28 , H01L21/8246 , H01L21/84 , H01L27/115 , H01L29/78 , H01L21/8242
CPC分类号： G11C11/22 , H01L21/28291 , H01L21/84 , H01L27/11502 , H01L27/11585 , H01L27/1159 , H01L29/78391 , G11C11/223 , Y10S438/957
摘要： A method of forming the FEM cell semi-conductor structure includes forming a device area for the ferroelectric memory (FEM) gate unit on a silicon substrate. Appropriate impurities are implanted into the device area to form conductive channels, for use as a source junction region, a gate junction region and a drain junction region. A FEM cell includes a FEM gate unit formed on the substrate. A gate junction region is formed between the source junction region and the drain junction region for the FEM gate unit on the FEM gate unit device area, which FEM gate unit includes a lower metal layer, a ferroelectric (FE) layer, and an upper metal layer. A shallow junction layer is formed between the FEM gate unit and the gate junction region, as another conductive channel, which extends into the drain junction region. The FEM gate unit is spaced apart from the source region and the drain region, as is the conductive channel between the FEM gate unit and the gate junction region. Formation of the various conductive channels may take place at various stages of the manufacture, depending on what other devices are built on the substrate, and depending on the efficiencies of the various orders of construction. The structure of the FEM cell semiconductor includes a substrate, which may be a bulk silicon substrate or an SOI-type substrate. Conductive channels of two types are located above the substrate.
摘要翻译：形成FEM单元半导体结构的方法包括在硅衬底上形成用于铁电存储器（FEM）栅极单元的器件区域。将合适的杂质注入器件区域以形成导电沟道，用作源极结区域，栅极结区域和漏极结区域。 FEM单元包括形成在基板上的FEM门单元。在FEM栅极单元器件区域上的FEM栅极单元的源极连接区域和漏极结区域之间形成栅极结区域，该FEM栅极单元包括下部金属层，铁电（FE）层和上部金属层。在FEM栅极单元和栅极结区域之间形成浅接合层，作为延伸到漏极结区域的另一个导电沟道。有限元门单元与源极区和漏极区间隔开，也就是FEM门单元和栅极结区之间的导电沟道。各种导电通道的形成可以在制造的各个阶段进行，这取决于衬底上构建的其它器件，以及各种施工顺序的效率。 FEM单元半导体的结构包括可以是体硅基板或SOI型基板的基板。两种类型的导电通道位于基板上方。

4. 发明授权

US5962884A Single transistor ferroelectric memory cell with asymmetrical ferroelectric polarization and method of making the same 失效
标题翻译：具有不对称铁电极化的单晶体铁电存储器单元及其制造方法
公开(公告)号：US5962884A
公开(公告)日：1999-10-05
申请号：US905380
申请日：1997-08-04
申请人： Sheng Teng Hsu , Jong Jan Lee
发明人： Sheng Teng Hsu , Jong Jan Lee
IPC分类号： G11C11/22 , H01L21/28 , H01L21/8246 , H01L21/84 , H01L27/115 , H01L29/78 , H01L29/76
CPC分类号： H01L21/84 , G11C11/22 , H01L21/28291 , H01L27/11502 , H01L27/11585 , H01L27/1159 , H01L29/78391 , G11C11/223
摘要： A method of forming a semiconductor structure having a ferroelectric memory (FEM) gate unit on a silicon substrate includes implanting doping impurities of a first type into the substrate to form a conductive channel of a first type, implanting doping impurities of a second type in the conductive channel of the first type to form a conductive channel well of a second type, implanting doping impurities of a third type in the conductive channel well of the second type to form a conductive channel of a third type for use as a gate junction region, implanting doping impurities of a fourth type in the conductive channel sub-well of the third type on either side of the gate junction region to form plural conductive channels of a fourth type for use as a source junction region and a drain junction region; and depositing an FEM gate unit over the gate junction region. A ferroelectric memory cell includes a silicon substrate of a first conductive type, a well structure of a second conductive type formed in the substrate, a structure of a third conductive type formed in the well structure, for use as a gate junction region. A source junction region and a drain junction region are located in the sub-well on either side of the gate junction region, doped to form conductive channels of a fourth type. A FEM gate unit overlays the conductive channel of the third type. An insulating layer overlays the junction regions, the FEM gate unit and the substrate. Suitable electrodes are connected to the various active regions in the memory cell.
摘要翻译：在硅衬底上形成具有铁电存储（FEM）栅极单元的半导体结构的方法包括将第一类型的掺杂杂质注入到衬底中以形成第一类型的导电沟道，将第二类型的掺杂杂质注入到所述第一类型的导电沟道形成第二类型的导电沟道阱，在所述第二类型的导电沟道阱中注入第三类型的掺杂杂质以形成用作栅极结区域的第三类型的导电沟道，在栅极结区域的任一侧上在第三类型的导电通道子阱中注入第四类型的掺杂杂质以形成用作源极结区域和漏极结区域的第四类型的多个导电沟道; 以及在栅极结区域上沉积FEM栅极单元。铁电存储单元包括第一导电类型的硅衬底，形成在衬底中的第二导电类型的阱结构，形成在阱结构中的第三导电类型的结构，用作栅极结区域。源极结区域和漏极结区域位于栅极结区域的任一侧的子阱中，被掺杂以形成第四类型的导电沟道。 FEM门单元覆盖第三类导电通道。绝缘层覆盖了连接区域，FEM栅极单元和衬底。合适的电极连接到存储单元中的各种有源区。

5. 发明授权

US5910673A Locos MOS device for ESD protection 失效
标题翻译： Locos MOS器件用于ESD保护
公开(公告)号：US5910673A
公开(公告)日：1999-06-08
申请号：US984801
申请日：1997-12-04
申请人： Sheng Teng Hsu , Katsumasa Fujii , Hidechika Kawazoe , Jong Jan Lee
发明人： Sheng Teng Hsu , Katsumasa Fujii , Hidechika Kawazoe , Jong Jan Lee
IPC分类号： H01L29/78 , H01L21/8234 , H01L27/02 , H01L27/088 , H01L23/62
CPC分类号： H01L27/0266 , Y10S438/981
摘要： A MOS transistor having a multilevel gate oxide layer is provided for use in an ESD protection circuit. A thick gate oxide layer near the drain insures that the transistor has a relatively large drain to gate breakdown voltage. A thin gate oxide layer near the source permits the gate voltage to turn the transistor on and off with rapid switching speeds. The thick portion of the MOS transistor multilevel gate oxide layer is formed with a local oxidation of silicon (LOCOS) process, while the thin gate layer is formed in a separate step. An ESD protection circuit and method for fabricating the above-mentioned multilevel gate oxide layer MOS transistor are also provided.
摘要翻译：提供具有多电平栅氧化层的MOS晶体管用于ESD保护电路中。在漏极附近的厚栅极氧化层确保晶体管具有相对较大的漏极到栅极击穿电压。靠近源极的薄栅极氧化层允许栅极电压以快速的开关速度开启和关闭晶体管。 MOS晶体管多电平栅极氧化物层的厚部分由硅（LOCOS）工艺的局部氧化形成，而薄栅极层在单独的步骤中形成。还提供了用于制造上述多电平栅极氧化物层MOS晶体管的ESD保护电路和方法。

6. 发明授权

US06649963B1 Ferroelectric memory cell for VLSI RAM 失效
标题翻译：用于VLSI RAM的铁电存储单元
公开(公告)号：US06649963B1
公开(公告)日：2003-11-18
申请号：US09455262
申请日：1999-12-06
申请人： Sheng Teng Hsu , Jong Jan Lee
发明人： Sheng Teng Hsu , Jong Jan Lee
IPC分类号： H01L27108
CPC分类号： H01L27/11502 , G11C11/22 , G11C11/223 , H01L21/28291 , H01L21/84 , H01L27/11585 , H01L27/1159 , H01L29/78391
摘要： A method of forming a semiconductor memory device on a silicon substrate includes implanting doping impurities of a first type in the silicon substrate to form a conductive channel of a first type for use as a gate junction region, forming a MOS capacitor on the conductive channel of the first type, depositing an FEM capacitor over less than the entire area of the MOS capacitor, thereby forming a stacked gate unit, implanting doping impurities of a second type in the silicon substrate on either side of the gate junction region to form a conductive channel of a second type for use as a source junction region and a drain junction region, and depositing an insulating structure about the FEM gate unit. A ferroelectric memory (FEM) cell constructed according to the invention includes a silicon substrate, a gate region located in said substrate, a source junction region and a drain junction region located on either side of the gate region, a MOS capacitor, a FEM capacitor, wherein the FEM capacitor is stacked on and overlays only a portion of the MOS capacitor, thereby forming, with the MOS capacitor, a stacked gate unit.
摘要翻译：在硅衬底上形成半导体存储器件的方法包括在硅衬底中注入第一类型的掺杂杂质以形成用作栅极结区域的第一类型的导电沟道，在导电沟道上形成MOS电容器第一类型，在小于MOS电容器的整个区域上沉积FEM电容器，从而形成堆叠栅极单元，在栅极结区域的任一侧上在硅衬底中注入第二类型的掺杂杂质以形成导电沟道用作源极结区域和漏极结区域的第二类型，以及围绕FEM栅极单元沉积绝缘结构。根据本发明构造的铁电存储器（FEM）单元包括硅衬底，位于所述衬底，位于栅极区两侧的源极结区域和漏极结区域，MOS电容器，FEM电容器，其中所述有机帽电容器堆叠在MOS电容器的一部分上并覆盖，从而与MOS电容器形成堆叠的栅极单元。

7. 发明授权

US6011285A C-axis oriented thin film ferroelectric transistor memory cell and method of making the same 失效
标题翻译： C轴取向薄膜铁电晶体管存储单元及其制作方法
公开(公告)号：US6011285A
公开(公告)日：2000-01-04
申请号：US2364
申请日：1998-01-02
申请人： Sheng Teng Hsu , Jong Jan Lee , Chien Hsiung Peng
发明人： Sheng Teng Hsu , Jong Jan Lee , Chien Hsiung Peng
IPC分类号： H01L21/8247 , C23C16/40 , H01L21/02 , H01L21/316 , H01L21/8242 , H01L21/8246 , H01L27/10 , H01L27/105 , H01L27/108 , H01L29/51 , H01L29/78 , H01L29/788 , H01L29/792
CPC分类号： H01L28/55 , C23C16/40 , H01L21/31604 , H01L21/31691 , H01L29/516 , H01L29/78391
摘要： The structure of a c-axis FEM cell semiconductor includes a silicon substrate; a source junction region and a drain junction region located in the substrate; a gate junction region located between the source junction region and the drain junction region; a FEM gate unit including a lower electrode, a c-axis oriented Pb.sub.5 Ge.sub.3 O.sub.11 FE layer and an upper electrode; wherein the FEM gate unit is sized on the gate junction region such that any edge of said FEM gate unit is a distance "D" from the edges of the source junction region and the drain junction region; an insulating layer, having an upper surface, overlying the junction regions, the FEM gate unit and the substrate; and source, drain and gate electrodes.
摘要翻译： c轴FEM单元半导体的结构包括硅衬底; 源极结区域和位于衬底中的漏极结区域; 位于源极结区域和漏极结区域之间的栅极结区域; 包括下电极，c轴取向Pb5Ge3O11FE层和上电极的FEM门单元; 其中所述FEM门单元的尺寸设置在所述栅极结区域上，使得所述FEM栅极单元的任何边缘距离源极结区域和漏极结区域的边缘为距离“D” 绝缘层，具有覆盖接合区域的上表面，FEM门单元和衬底; 以及源极，漏极和栅极。

8. 发明授权

US5731608A One transistor ferroelectric memory cell and method of making the same 失效
标题翻译：一种晶体管铁电存储单元及其制造方法
公开(公告)号：US5731608A
公开(公告)日：1998-03-24
申请号：US812579
申请日：1997-03-07
申请人： Sheng Teng Hsu , Jong Jan Lee
发明人： Sheng Teng Hsu , Jong Jan Lee
IPC分类号： G11C11/22 , H01L21/28 , H01L21/8246 , H01L21/84 , H01L27/115 , H01L29/78 , H01L21/8242
CPC分类号： H01L27/11502 , G11C11/22 , H01L21/28291 , H01L21/84 , H01L27/11585 , H01L27/1159 , H01L29/78391 , G11C11/223
摘要： A method of forming a semi-conductor structure forming, on a prepared substrate, a ferroelectric memory (FEM) gate unit. A gate junction region is formed between the source junction region and the drain junction region for the FEM gate unit on a FEM gate unit device area, which FEM gate unit includes a lower metal layer, a ferroelectric (FE) layer, and an upper metal layer, and which is formed on a conductive channel precursor. The structure of the semiconductor includes a substrate, which may be either bulk silicon or SOI-type silicon, conductive channels of first and second type formed above the substrate, an FEM gate unit formed above a channel region, wherein the FEM gate unit includes a lower metal layer, an FE layer, and an upper metal layer, and wherein a conductive channel of a second type is formed under the FEM gate unit.
摘要翻译：一种形成半导体结构的方法，在制备的基板上形成铁电存储（FEM）门单元。在FEM栅极单元器件区域上的FEM栅极单元的源极结和区域之间形成栅极结区，该有限元栅极单元包括下部金属层，铁电（FE）层和上部金属层，并且其形成在导电通道前体上。半导体的结构包括可以是体硅或SOI型硅的衬底，在衬底上形成的第一和第二类型的导电沟道，形成在沟道区上方的FEM门单元，其中FEM门单元包括下金属层，FE层和上金属层，并且其中在FEM门单元下方形成第二类型的导电沟道。

9. 发明授权

US6146904A Method of making a two transistor ferroelectric memory cell 有权
标题翻译：制造双晶体管铁电存储单元的方法
公开(公告)号：US6146904A
公开(公告)日：2000-11-14
申请号：US292064
申请日：1999-04-14
申请人： Sheng Teng Hsu , Jong Jan Lee
发明人： Sheng Teng Hsu , Jong Jan Lee
IPC分类号： G11C11/22 , H01L21/28 , H01L21/8246 , H01L21/84 , H01L27/115 , H01L29/78 , H01G7/06
CPC分类号： H01L27/11502 , G11C11/22 , H01L21/28291 , H01L21/84 , H01L27/11585 , H01L27/1159 , H01L29/78391 , G11C11/223
摘要： The method of forming the two transistor semi-conductor structure includes forming a device area for a MOS transistor and for a ferroelectric memory (FEM) gate unit on a silicon substrate. A conventional MOS transistor is formed on the substrate. A FEM cell includes a FEM gate unit formed on the substrate, either above or along side of the MOS transistor. The FEM gate unit is spaced apart from a source region and a drain region. Formation of the various conductive channels may take place at various stages of the manufacture, depending on what other devices are built on the substrate, and depending on the efficiencies of the various orders of construction. The structure of the two transistor semiconductor includes a silicon substrate, which may be a bulk silicon substrate or an SOI-type substrate. Conductive channels of three types are located above the substrate. A FEM gate unit is located above a gate region, either over or along side of a conventional MOS transistor, wherein the FEM gate unit includes a lower metal layer, an FE layer, and an upper metal layer.
摘要翻译：形成双晶体管半导体结构的方法包括在硅衬底上形成用于MOS晶体管的器件区域和铁电存储器（FEM）栅极单元。在基板上形成常规的MOS晶体管。有限元单元包括形成在衬底上的FEM门单元，位于MOS晶体管的上方或旁边。 FEM门单元与源极区域和漏极区域间隔开。各种导电通道的形成可以在制造的各个阶段进行，这取决于衬底上构建的其它器件，以及各种施工顺序的效率。两晶体管半导体的结构包括可以是体硅衬底或SOI型衬底的硅衬底。三种导电通道位于基板上方。 FEM栅极单元位于常规MOS晶体管的上方或旁边的栅极区域上方，其中FEM栅极单元包括下部金属层，FE层和上部金属层。

10. 发明授权

US5942776A Shallow junction ferroelectric memory cell and method of making the same 失效
标题翻译：浅结铁电记忆单元及其制作方法
公开(公告)号：US5942776A
公开(公告)日：1999-08-24
申请号：US869534
申请日：1997-06-06
申请人： Sheng Teng Hsu , Jong Jan Lee
发明人： Sheng Teng Hsu , Jong Jan Lee
IPC分类号： G11C11/22 , H01L21/28 , H01L21/8246 , H01L21/84 , H01L27/115 , H01L29/78 , H01L21/8242
CPC分类号： G11C11/22 , H01L21/28291 , H01L21/84 , H01L27/11502 , H01L27/11585 , H01L27/1159 , H01L29/78391 , G11C11/223 , Y10S438/957
摘要： A method of forming a FEM cell semi-conductor structure includes forming a device area for the ferroelectric memory (FEM) gate unit on a silicon substrate. Appropriate impurities are implanted into the device area to form conductive channels, for use as a source junction region, a gate junction region and a drain junction region. A FEM cell includes a FEM gate unit formed on the substrate. A gate junction region is formed between the source junction region and the drain junction region for the FEM gate unit on the FEM gate unit device area, which FEM gate unit includes a lower metal layer, a ferroelectric (FE) layer, and an upper metal layer. A shallow junction layer is formed between the FEM gate unit and the gate junction region, as another conductive channel. The FEM gate unit is spaced apart from the source region and the drain region, as is the conductive channel between the FEM gate unit and the gate junction region. Formation of the various conductive channels may take place at various stages of the manufacture, depending on what other devices are built on the substrate, and depending on the efficiencies of the various orders of construction. The structure of the FEM cell semiconductor includes a substrate, which may be a bulk silicon substrate or an SOI-type substrate. Conductive channels of a first and a second type are located on the substrate.
摘要翻译：形成FEM单元半导体结构的方法包括在硅衬底上形成用于铁电存储器（FEM）栅极单元的器件区域。将合适的杂质注入器件区域以形成导电沟道，用作源极结区域，栅极结区域和漏极结区域。 FEM单元包括形成在基板上的FEM门单元。在FEM栅极单元器件区域上的FEM栅极单元的源极连接区域和漏极结区域之间形成栅极结区域，该FEM栅极单元包括下部金属层，铁电（FE）层和上部金属层。作为另一个导电通道，在FEM栅极单元和栅极结区域之间形成浅结层。有限元门单元与源极区和漏极区间隔开，也就是FEM门单元和栅极结区之间的导电沟道。各种导电通道的形成可以在制造的各个阶段进行，这取决于衬底上构建的其它器件，以及各种施工顺序的效率。 FEM单元半导体的结构包括可以是体硅基板或SOI型基板的基板。第一和第二类型的导电通道位于基板上。

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