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1. 发明授权

US5383088A Storage capacitor with a conducting oxide electrode for metal-oxide dielectrics 失效
标题翻译：具有用于金属氧化物电介质的导电氧化物电极的储存电容器
公开(公告)号：US5383088A
公开(公告)日：1995-01-17
申请号：US103620
申请日：1993-08-09
申请人： Jonathan D. Chapple-Sokol , Richard A. Conti , Jeffrey P. Gambino
发明人： Jonathan D. Chapple-Sokol , Richard A. Conti , Jeffrey P. Gambino
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01G1/01
CPC分类号： H01L27/10852 , H01L28/40
摘要： A capacitor having a high dielectric constant and method of making the same is disclosed. The capacitor comprises a bottom electrode comprising a conductive oxide deposited upon a substrate by chemical vapor deposition. A dielectric layer having a high dielectric constant is deposited upon the conductive oxide. Lastly, a counter electrode is formed upon the dielectric layer.
摘要翻译：公开了具有高介电常数的电容器及其制造方法。电容器包括底部电极，其包括通过化学气相沉积沉积在衬底上的导电氧化物。具有高介电常数的介电层沉积在导电氧化物上。最后，在电介质层上形成对电极。

2. 发明授权

US06232222B1 Method of eliminating a critical mask using a blockout mask and a resulting semiconductor structure 失效
标题翻译：使用阻挡掩模和所得半导体结构消除临界掩模的方法
公开(公告)号：US06232222B1
公开(公告)日：2001-05-15
申请号：US09395418
申请日：1999-09-14
申请人： Michael Armacost , Richard A. Conti , Jeffrey P. Gambino , Jeremy K. Stephens
发明人： Michael Armacost , Richard A. Conti , Jeffrey P. Gambino , Jeremy K. Stephens
IPC分类号： H01L214763
CPC分类号： H01L21/76897 , H01L21/31144 , H01L27/10873 , H01L27/10894
摘要： A method of forming a semiconductor structure may include forming a semiconductor substrate having an array region and a support region, forming a semiconductor substrate and a gate stack over the support region of the substrate and applying a critical mask over the support region and the array region. The critical mask may have a first opening at an area corresponding to the array region and a second opening at an area corresponding to the support region. Contact holes may be formed in a glass layer at areas corresponding to the first and second opening. After removing the critical mask, a first blockout mask may be applied over the array region and a first conductive type dopant may be added to exposed polysilicon corresponding to openings of the blockout mask or gate contacts may be formed.
摘要翻译：形成半导体结构的方法可以包括形成具有阵列区域和支撑区域的半导体衬底，在衬底的支撑区域上形成半导体衬底和栅叠层，并在衬底区域和阵列区域上施加临界掩模。临界掩模可以在对应于阵列区域的区域处具有第一开口，并且在对应于支撑区域的区域处具有第二开口。可以在对应于第一和第二开口的区域的玻璃层中形成接触孔。在去除临界掩模之后，可以在阵列区域上施加第一堵塞掩模，并且可以形成第一导电型掺杂剂，以对应于封闭掩模的开口或栅极触点形成对应于暴露的多晶硅。

3. 发明授权

US5939335A Method for reducing stress in the metallization of an integrated circuit 失效
标题翻译：降低集成电路金属化应力的方法
公开(公告)号：US5939335A
公开(公告)日：1999-08-17
申请号：US3107
申请日：1998-01-06
申请人： Kenneth C. Arndt , Richard A. Conti , David M. Dobuzinsky , Laertis Economikos , Jeffrey P. Gambino , Peter D. Hoh , Chandrasekhar Narayan
发明人： Kenneth C. Arndt , Richard A. Conti , David M. Dobuzinsky , Laertis Economikos , Jeffrey P. Gambino , Peter D. Hoh , Chandrasekhar Narayan
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/3205 , H01L21/3213 , H01L21/768 , H01L21/336
CPC分类号： H01L21/76804 , H01L21/32136 , H01L21/76835 , H01L21/76885
摘要： The stresses commonly induced in the dielectrics of integrated circuits manufactured using metal patterning methods, such as reactive ion etching (RIE) and damascene techniques, can be reduced by rounding the lower corners associated with the features which are formed as part of the integrated circuit (e.g., the interconnects) before applying the outer (i.e., passivation) layer. In connection with the formation of metal lines patterned by a metal RIE process, such corner rounding can be achieved using a two-step metal etching process including a first step which produces a vertical sidewall and a second step which tapers lower portions of the vertical sidewall or which produces a tapered spacer along the lower portions of the vertical sidewall. This results in a rounded bottom corner which improves the step coverage of the overlying dielectric, in turn eliminating the potential for cracks. For metal lines patterned by damascene, such corner rounding can be achieved using a two-step trench etching process including a first step which produces a vertical sidewall, and a second step which produces a tapered sidewall along lower portions of the vertical sidewall.
摘要翻译：通过使与金属图案化方法（例如反应离子蚀刻（RIE）和镶嵌技术）一起制造的集成电路的电介质中通常感应的应力可以通过将与形成为集成电路的一部分的特征相关联的下角在施加外部（即钝化）层之前，例如，互连）。关于通过金属RIE工艺形成的金属线的形成，可以使用包括产生垂直侧壁的第一步骤和使垂直侧壁的下部逐渐变细的第二步骤的两步金属蚀刻工艺来实现这种角圆化或者沿着垂直侧壁的下部产生锥形间隔物。这导致圆角的底角，其改善了上覆电介质的台阶覆盖，从而消除了裂纹的可能性。对于由大马士革图案化的金属线，可以使用包括产生垂直侧壁的第一步骤的两步沟槽蚀刻工艺，以及沿着垂直侧壁的下部产生锥形侧壁的第二步骤来实现这种角落圆化。

4. 发明授权

US06208008B1 Integrated circuits having reduced stress in metallization 失效
标题翻译：集成电路在金属化中具有降低的应力
公开(公告)号：US06208008B1
公开(公告)日：2001-03-27
申请号：US09260702
申请日：1999-03-02
申请人： Kenneth C. Arndt , Richard A. Conti , David M. Dobuzinsky , Laertis Economikos , Jeffrey P. Gambino , Peter D. Hoh , Chandrasekhar Narayan
发明人： Kenneth C. Arndt , Richard A. Conti , David M. Dobuzinsky , Laertis Economikos , Jeffrey P. Gambino , Peter D. Hoh , Chandrasekhar Narayan
IPC分类号： H01L2941
CPC分类号： H01L21/76804 , H01L21/32136 , H01L21/76835 , H01L21/76885
摘要： The stresses commonly induced in the dielectrics of integrated circuits manufactured using metal patterning methods, such as reactive ion etching (RIE) and damascene techniques, can be reduced by rounding the lower corners associated with the features which are formed as part of the integrated circuit (e.g., the interconnects) before applying the outer (i.e., passivation) layer. In connection with the formation of metal lines patterned by a metal RIE process, such corner rounding can be achieved using a two-step metal etching process including a first step which produces a vertical sidewall and a second step which tapers lower portions of the vertical sidewall or which produces a tapered spacer along the lower portions of the vertical sidewall. This results in a rounded bottom corner which improves the step coverage of the overlying dielectric, in turn eliminating the potential for cracks. For metal lines patterned by damascene, such corner rounding can be achieved using a two-step trench etching process including a first step which produces a vertical sidewall, and a second step which produces a tapered sidewall along lower portions of the vertical sidewall.
摘要翻译：通过使与金属图案化方法（例如反应离子蚀刻（RIE）和镶嵌技术）一起制造的集成电路的电介质中通常引起的应力可以通过将与形成为集成电路的一部分的特征相关联的下角在施加外部（即钝化）层之前，例如，互连）。关于通过金属RIE工艺形成的金属线的形成，可以使用包括产生垂直侧壁的第一步骤和使垂直侧壁的下部逐渐变细的第二步骤的两步金属蚀刻工艺来实现这种角圆化或者沿着垂直侧壁的下部产生锥形间隔物。这导致圆角的底角，其改善了上覆电介质的台阶覆盖，从而消除了裂纹的可能性。对于由大马士革图案化的金属线，可以使用包括产生垂直侧壁的第一步骤的两步沟槽蚀刻工艺，以及沿着垂直侧壁的下部产生锥形侧壁的第二步骤来实现这种角落圆化。

5. 发明授权

US09058455B2 Backside integration of RF filters for RF front end modules and design structure 有权
标题翻译：用于RF前端模块的RF滤波器的背面集成和设计结构
公开(公告)号：US09058455B2
公开(公告)日：2015-06-16
申请号：US13354705
申请日：2012-01-20
申请人： James W. Adkisson , Panglijen Candra , Thomas J. Dunbar , Jeffrey P. Gambino , Mark D. Jaffe , Anthony K. Stamper , Randy L. Wolf
发明人： James W. Adkisson , Panglijen Candra , Thomas J. Dunbar , Jeffrey P. Gambino , Mark D. Jaffe , Anthony K. Stamper , Randy L. Wolf
IPC分类号： G06F17/50 , H01L21/768 , H01L23/48 , H03H9/64 , H01L23/00 , H01L27/06 , H01L49/02 , H01L23/66 , H01L25/16
CPC分类号： H01L41/293 , G06F17/5063 , G06F17/5068 , H01L21/76898 , H01L23/481 , H01L23/66 , H01L24/03 , H01L24/05 , H01L24/24 , H01L25/16 , H01L27/0694 , H01L28/40 , H01L41/0815 , H01L41/25 , H01L2224/03009 , H01L2224/0401 , H01L2224/04105 , H01L2224/0557 , H01L2224/05572 , H01L2224/06181 , H01L2224/12105 , H01L2224/14181 , H01L2224/16145 , H01L2224/24145 , H01L2225/06548 , H03H9/64
摘要： A design structure for an integrated radio frequency (RF) filter on a backside of a semiconductor substrate includes: a device on a first side of a substrate; a radio frequency (RF) filter on a backside of the substrate; and at least one substrate conductor extending from the front side of the substrate to the backside of the substrate and electrically coupling the RF filter to the device.
摘要翻译：在半导体衬底的背面上的集成射频（RF）滤波器的设计结构包括：在衬底的第一侧上的器件; 在衬底的背面上的射频（RF）滤波器; 以及至少一个衬底导体，其从所述衬底的前侧延伸到所述衬底的所述背面并将所述RF滤波器电耦合到所述器件。

6. 发明授权

US08946013B2 Lateral diffusion field effect transistor with drain region self-aligned to gate electrode 有权
标题翻译：侧向扩散场效应晶体管，漏极区自对准至栅电极
公开(公告)号：US08946013B2
公开(公告)日：2015-02-03
申请号：US13364663
申请日：2012-02-02
申请人： Natalie B. Feilchenfeld , Jeffrey P. Gambino , Xuefeng Liu , Benjamin T. Voegeli , Steven H. Voldman , Michael J. Zierak
发明人： Natalie B. Feilchenfeld , Jeffrey P. Gambino , Xuefeng Liu , Benjamin T. Voegeli , Steven H. Voldman , Michael J. Zierak
IPC分类号： H01L21/00 , H01L21/265 , H01L29/66 , H01L29/78 , H01L29/10
CPC分类号： H01L21/26586 , H01L21/26513 , H01L29/1045 , H01L29/6656 , H01L29/66659 , H01L29/7835
摘要： A disposable structure displaced from an edge of a gate electrode and a drain region aligned to the disposable structure is formed. Thus, the drain region is self-aligned to the edge of the gate electrode. The disposable structure may be a disposable spacer, or alternately, the disposable structure may be formed simultaneously with, and comprise the same material as, a gate electrode. After formation of the drain regions, the disposable structure is removed. The self-alignment of the drain region to the edge of the gate electrode provides a substantially constant drift distance that is independent of any overlay variation of lithographic processes.
摘要翻译：形成从栅电极的边缘排列的一次性结构和与一次性结构对准的漏区。因此，漏极区域与栅电极的边缘自对准。一次性结构可以是一次性间隔件，或者替代地，一次性结构可以与栅电极同时形成并且包括与栅电极相同的材料。在形成漏极区域之后，一次性结构被去除。漏极区域到栅电极的边缘的自对准提供了与光刻工艺的任何叠加变化无关的基本恒定的漂移距离。

7. 发明授权

US08927869B2 Semiconductor structures and methods of manufacture 有权
标题翻译：半导体结构及制造方法
公开(公告)号：US08927869B2
公开(公告)日：2015-01-06
申请号：US13444343
申请日：2012-04-11
申请人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Zhong-Xiang He , Christopher D. Muzzy , Wolfgang Sauter , Timothy D. Sullivan
发明人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Zhong-Xiang He , Christopher D. Muzzy , Wolfgang Sauter , Timothy D. Sullivan
IPC分类号： H05K1/00
CPC分类号： H01L24/05 , H01B3/306 , H01B3/307 , H01L21/02118 , H01L21/76877 , H01L24/03 , H01L2224/02166 , H01L2224/03462 , H01L2224/03831 , H01L2224/04042 , H01L2224/05009 , H01L2224/05124 , H01L2224/05624 , H01L2924/00014 , H01L2224/48
摘要： Wire-bonded semiconductor structures using organic insulating material and methods of manufacture are disclosed. The method includes forming a metal wiring layer in an organic insulator layer. The method further includes forming a protective layer over the organic insulator layer. The method further includes forming a via in the organic insulator layer over the metal wiring layer. The method further includes depositing a metal layer in the via and on the protective layer. The method further includes patterning the metal layer with an etch chemistry that is damaging to the organic insulator layer.
摘要翻译：公开了使用有机绝缘材料的引线键合半导体结构和制造方法。该方法包括在有机绝缘体层中形成金属布线层。该方法还包括在有机绝缘体层上形成保护层。该方法还包括在金属布线层上的有机绝缘体层中形成通孔。该方法还包括在通孔中和保护层上沉积金属层。该方法还包括用对有机绝缘体层有害的蚀刻化学物图案化金属层。

8. 发明授权

US08766439B2 Integrated circuit chip with pyramid or cone-shaped conductive pads for flexible C4 connections and a method of forming the integrated circuit chip 失效
标题翻译：具有用于灵活C4连接的金字塔或锥形导电焊盘的集成电路芯片和形成集成电路芯片的方法
公开(公告)号：US08766439B2
公开(公告)日：2014-07-01
申请号：US12634741
申请日：2009-12-10
申请人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter , Timothy D. Sullivan
发明人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter , Timothy D. Sullivan
IPC分类号： H01L23/12
CPC分类号： H01L24/11 , H01L23/49816 , H01L24/13 , H01L24/81 , H01L2224/1147 , H01L2224/11901 , H01L2224/11902 , H01L2224/13018 , H01L2224/13019 , H01L2224/13023 , H01L2224/13076 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/1357 , H01L2224/136 , H01L2224/13609 , H01L2224/13611 , H01L2224/13613 , H01L2224/13618 , H01L2224/1362 , H01L2224/13639 , H01L2224/13647 , H01L2224/1601 , H01L2224/16237 , H01L2224/81191 , H01L2224/81193 , H01L2224/81801 , H01L2924/00013 , H01L2924/01005 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01046 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/351 , H01L2924/00014 , H01L2924/01028 , H01L2224/13099 , H01L2924/00012
摘要： Disclosed is a chip and method of forming the chip with improved conductive pads that allow for flexible C4 connections with a chip carrier or with another integrated circuit chip. The pads have a three-dimensional geometric shape (e.g., a pyramid or cone shape) with a base adjacent to the surface of the chip, a vertex opposite the base and, optionally, mushroom-shaped cap atop the vertex. Each pad can include a single layer of conductive material or multiple layers of conductive material (e.g., a wetting layer stacked above a non-wetting layer). The pads can be left exposed to allow for subsequent connection to corresponding solder bumps on a chip carrier or a second chip. Alternatively, solder balls can be positioned on the conductive pads to allow for subsequent connection to corresponding solder-paste filled openings on a chip carrier or a second chip.
摘要翻译：公开了一种用改进的导电焊盘形成芯片的芯片和方法，其允许与芯片载体或另一个集成电路芯片的柔性C4连接。垫具有三维几何形状（例如，金字塔或锥形），其具有与芯片表面相邻的基部，与基部相对的顶点以及可选地在顶点顶部的蘑菇形帽。每个焊盘可以包括单层导电材料或多层导电材料（例如，堆叠在非润湿层上方的润湿层）。焊盘可以被暴露以允许随后连接到芯片载体或第二芯片上的相应焊料凸块。或者，焊球可以定位在导电焊盘上，以允许随后连接到芯片载体或第二芯片上相应的焊膏填充的开口。

9. 发明授权

US08765595B2 Thick on-chip high-performance wiring structures 有权
标题翻译：厚片上高性能布线结构
公开(公告)号：US08765595B2
公开(公告)日：2014-07-01
申请号：US13345120
申请日：2012-01-06
申请人： Edward C. Cooney, III , Jeffrey P. Gambino , Zhong-Xiang He , Tom C. Lee , Xiao H. Liu
发明人： Edward C. Cooney, III , Jeffrey P. Gambino , Zhong-Xiang He , Tom C. Lee , Xiao H. Liu
IPC分类号： H01L21/4763
CPC分类号： H01L23/5227 , H01L21/76883 , H01L23/5283 , H01L23/5329 , H01L23/53295 , H01L28/10 , H01L2924/0002 , H01L2924/00
摘要： Methods for fabricating a back-end-of-line (BEOL) wiring structure, BEOL wiring structures, and design structures for a BEOL wiring structure. The BEOL wiring may be fabricated by forming a first wire in a dielectric layer and annealing the first wire in an oxygen-free atmosphere. After the first wire is annealed, a second wire is formed in vertical alignment with the first wire. A final passivation layer, which is comprised of an organic material such as polyimide, is formed that covers an entirety of a sidewall of the second wire.
摘要翻译： BEOL布线结构的制造方法，BEOL布线结构以及BEOL布线结构的设计结构。 BEOL布线可以通过在电介质层中形成第一布线并在无氧气氛中退火第一布线来制造。在第一线退火之后，形成与第一线垂直对准的第二线。形成由诸如聚酰亚胺的有机材料组成的最终钝化层，其覆盖第二线的整个侧壁。

10. 发明授权

US08679863B2 Fine tuning highly resistive substrate resistivity and structures thereof 失效
标题翻译：微调高电阻衬底电阻率及其结构
公开(公告)号：US08679863B2
公开(公告)日：2014-03-25
申请号：US13420637
申请日：2012-03-15
申请人： Jeffrey P. Gambino , Derrick Liu , Dale W. Martin , Gerd Pfeiffer
发明人： Jeffrey P. Gambino , Derrick Liu , Dale W. Martin , Gerd Pfeiffer
IPC分类号： H01L21/00
CPC分类号： H01L22/14 , H01L21/324 , H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： Methods are provided for fine tuning substrate resistivity. The method includes measuring a resistivity of a substrate after an annealing process, and fine tuning a subsequent annealing process to achieve a target resistivity of the substrate. The fine tuning is based on the measured resistivity.
摘要翻译：提供了微调衬底电阻率的方法。该方法包括测量退火处理之后的衬底的电阻率，并且微调随后的退火工艺以实现衬底的目标电阻率。微调基于测量的电阻率。

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