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1. 发明申请

US20070008784A1 Two-bit per I/O line write data bus for DDR1 and DDR2 operating modes in a DRAM 有权
标题翻译：在DRAM中为DDR1和DDR2工作模式写入数据总线的两位I / O线
公开(公告)号：US20070008784A1
公开(公告)日：2007-01-11
申请号：US11177537
申请日：2005-07-08
申请人： Jon Faue , Steve Eaton , Michael Murray
发明人： Jon Faue , Steve Eaton , Michael Murray
IPC分类号： G11C7/10
CPC分类号： G11C7/1078 , G11C7/1072 , G11C7/1093 , G11C7/1096
摘要： A data bus circuit for an integrated circuit memory includes a 4-bit bus per I/O pad that is used to connect the memory with an I/O block, but only two bits per I/O are utilized for writing. Four bits per I/O pad are used for reading. At every falling edge of an input data strobe, the last two bits are transmitted over the bus, which eliminates the need for the precise counting of input data strobe pulses. The data bus circuit is compatible with both DDR1 and DDR2 operating modes.
摘要翻译：用于集成电路存储器的数据总线电路包括用于将存储器与I / O块连接的每个I / O焊盘的4位总线，但每个I / O仅使用两位用于写入。使用四位每个I / O焊盘进行读取。在输入数据选通的每个下降沿，最后两位通过总线发送，这样就不需要精确计数输入数据选通脉冲。数据总线电路兼容DDR1和DDR2工作模式。

2. 发明申请

US20080137462A1 TWO-BIT PER I/O LINE WRITE DATA BUS FOR DDR1 AND DDR2 OPERATING MODES IN A DRAM 审中-公开
标题翻译：用于DRAM中DDR1和DDR2操作模式的I / O线写入数据总线的两位
公开(公告)号：US20080137462A1
公开(公告)日：2008-06-12
申请号：US12020352
申请日：2008-01-25
申请人： Jon Allan Faue , Steve Eaton , Michael Murray
发明人： Jon Allan Faue , Steve Eaton , Michael Murray
IPC分类号： G11C7/00
CPC分类号： G11C7/1078 , G11C7/1072 , G11C7/1093 , G11C7/1096
摘要： A data bus circuit for an integrated circuit memory includes a 4-bit bus per I/O pad that is used to connect the memory with an I/O block, but only two bits per I/O are utilized for writing. Four bits per I/O pad are used for reading. At every falling edge of an input data strobe, the last two bits are transmitted over the bus, which eliminates the need for the precise counting of input data strobe pulses. The data bus circuit is compatible with both DDR1 and DDR2 operating modes.
摘要翻译：用于集成电路存储器的数据总线电路包括用于将存储器与I / O块连接的每个I / O焊盘的4位总线，但每个I / O仅使用两位用于写入。使用四位每个I / O焊盘进行读取。在输入数据选通的每个下降沿，最后两位通过总线发送，这样就不需要精确计数输入数据选通脉冲。数据总线电路兼容DDR1和DDR2工作模式。

3. 发明授权

US07349289B2 Two-bit per I/O line write data bus for DDR1 and DDR2 operating modes in a DRAM 有权
标题翻译：在DRAM中为DDR1和DDR2工作模式写入数据总线的两位I / O线
公开(公告)号：US07349289B2
公开(公告)日：2008-03-25
申请号：US11177537
申请日：2005-07-08
申请人： Jon Allan Faue , Steve Eaton , Michael Murray
发明人： Jon Allan Faue , Steve Eaton , Michael Murray
IPC分类号： G11C7/22 , G11C7/10 , G11C11/4093 , G11C11/4096
CPC分类号： G11C7/1078 , G11C7/1072 , G11C7/1093 , G11C7/1096
摘要： A data bus circuit for an integrated circuit memory includes a 4-bit bus per I/O pad that is used to connect the memory with an I/O block, but only two bits per I/O are utilized for writing. Four bits per I/O pad are used for reading. At every falling edge of an input data strobe, the last two bits are transmitted over the bus, which eliminates the need for the precise counting of input data strobe pulses. The data bus circuit is compatible with both DDR1 and DDR2 operating modes.
摘要翻译：用于集成电路存储器的数据总线电路包括用于将存储器与I / O块连接的每个I / O焊盘的4位总线，但每个I / O仅使用两位用于写入。使用四位每个I / O焊盘进行读取。在输入数据选通的每个下降沿，最后两位通过总线发送，这样就不需要精确计数输入数据选通脉冲。数据总线电路兼容DDR1和DDR2工作模式。

4. 发明申请

US20150240551A1 Tension Adjustable Retractable Screen Assembly 审中-公开
标题翻译：张力可调伸缩式屏幕组件
公开(公告)号：US20150240551A1
公开(公告)日：2015-08-27
申请号：US14634165
申请日：2015-02-27
申请人： Michael Murray
发明人： Michael Murray
IPC分类号： E06B3/44
CPC分类号： E06B9/581 , E06B9/582 , Y10T16/3797
摘要： A screen track assembly for mounting and tensioning a retractable screen across an opening, the assembly having a generally U-shaped outer track member having an opening; an inner track member received within the outer track member, the inner track member adapted to receive a retractable screen, the inner track member being movable relative to the outer track member; biasing members to present a biasing force to extend the inner track member toward the opening of the outer track member; and adjustable mechanical fasteners to fix the position of the inner track member relative to the outer track member such that the screen may be tightened or loosened as required for proper functionality.
摘要翻译：一种屏幕轨道组件，用于安装和张紧横跨开口的可伸缩屏幕，所述组件具有大致U形的外轨道构件，该外轨道构件具有开口; 内轨道构件，其容纳在所述外轨道构件内，所述内轨道构件适于接收可缩回的屏幕，所述内轨道构件可相对于所述外轨道构件移动; 偏置构件呈现偏置力以将内轨道构件朝向外轨道构件的开口延伸; 以及可调节的机械紧固件，以相对于外轨道构件固定内轨道构件的位置，使得屏幕可以根据正常功能所需而被拧紧或松动。

5. 发明申请

US20150053217A1 ELECTRONIC CIGARETTE 审中-公开
标题翻译：电子香烟
公开(公告)号：US20150053217A1
公开(公告)日：2015-02-26
申请号：US14063066
申请日：2014-06-11
申请人： Matthew Steingraber , Dabielle Steingraber , Michael Murray
发明人： Matthew Steingraber , Dabielle Steingraber , Michael Murray
IPC分类号： A24F47/00
CPC分类号： A24F47/008
摘要： An electronic cigarette with inlet air constructed and arranged to contact a delivery substance and minimize airflow over electronic components.
摘要翻译：具有入口空气的电子烟，其构造和布置成接触输送物质并使电子部件的气流最小化。

6. 发明申请

US20110225384A1 FLASH STORAGE PARTIAL PAGE CACHING 有权
标题翻译：闪存存储部分页面缓存
公开(公告)号：US20110225384A1
公开(公告)日：2011-09-15
申请号：US13116626
申请日：2011-05-26
申请人： Viet Ly , Michael Murray
发明人： Viet Ly , Michael Murray
IPC分类号： G06F12/02
CPC分类号： G11C16/0483 , G06F12/0246 , G06F2212/7203 , G11C11/5628 , G11C16/10
摘要： Methods and apparatus may operate to receive allocation requests from a processor configured to manage memory comprising a non-volatile memory device configurable as a plurality of blocks comprising a plurality of sectors, assign partial page blocks from the plurality of blocks for memory storage, fill some of the sectors by storing data bits associated with the allocation request in the at least one of the plurality of sectors, determine that the sectors are full, assigning a full page block from the plurality of blocks, and transfer the data bits associated with the allocation request from the partial page blocks to the full page block. Other apparatus, systems, and methods are disclosed.
摘要翻译：方法和装置可以操作以从配置成管理存储器的处理器接收分配请求，该存储器包括可配置为包括多个扇区的多个块的非易失性存储器件，从多个块中分配部分页块用于存储器存储，填充一些通过将与分配请求相关联的数据位存储在多个扇区中的至少一个扇区中，确定扇区是满的，从多个块分配全页块，并传送与分配相关联的数据位从部分页面块到全页块的请求。公开了其他装置，系统和方法。

7. 发明授权

US07886907B2 Vapor hydration of a hydrophilic product in a package 有权
标题翻译：包装中的亲水产品的蒸气水化
公开(公告)号：US07886907B2
公开(公告)日：2011-02-15
申请号：US12715879
申请日：2010-03-02
申请人： Michael Murray , Thomas H. Gilman , Sean Sweeney , Martin P. Creaven
发明人： Michael Murray , Thomas H. Gilman , Sean Sweeney , Martin P. Creaven
IPC分类号： B65D83/10 , B65D81/24 , A61B19/02 , A61M5/00 , A61M25/00
CPC分类号： A61M25/002 , A61M25/0009 , A61M25/0017 , A61M25/007 , A61M25/0111 , A61M2025/0046 , A61M2025/0681 , B65B5/04 , B65B7/02 , B65B55/22 , B65D81/22
摘要： A vapor hydrated packaged catheter assembly and method of manufacturing and distributing same includes a gas impermeable package housing a catheter within a catheter-receiving cavity. The catheter assembly has a hydrophilic coating applied to at least a portion of the outer surface of a catheter tube or shaft which may be surrounded by a sleeve to provide a no-touch, sure grip feature. The catheter assembly is disposed within the catheter receiving cavity of the package together with a limited amount of a vapor donating liquid provided as a source of vapor to activate the hydrophilic coating. The amount of vapor donating liquid is less than the amount that would otherwise be sufficient to cause a spill hazard. It may be loose liquid as a desired percentage of the volume of a tube-receiving portion of the catheter receiving cavity of the package, or it may be contained in a liquid sequestering element. The activation of at least some of the hydrophilic coating occurs solely by reason of exposure of the outer surface of the catheter to a vapor produced by the vapor donating liquid. The distribution of the catheter following manufacture is delayed for a time sufficient to permit the vapor to complete hydration of the entire hydrophilic coating on the surface.
摘要翻译：蒸气水合包装导管组件及其制造和分配方法包括将导管容纳在导管接收腔内的不透气包装。导管组件具有施加到导管管或轴的外表面的至少一部分的亲水涂层，导管管或轴的外表面可以由套筒包围以提供无接触的确定的抓握特征。导管组件与限定量的作为蒸气源提供的蒸气供应液体一起设置在包装的导管容纳腔内，以激活亲水涂层。蒸汽供应液体的量小于否则足以引起溢出危险的量。其可以是作为包装的导管接收腔的管接收部分的体积的所需百分比的松散液体，或者其可以包含在液体隔离元件中。至少一些亲水性涂层的活化仅仅由于将导管的外表面暴露于由蒸气供给液体产生的蒸汽而发生。制造后导管的分布延迟一段时间，足以允许蒸气完成表面上整个亲水涂层的水化。

8. 发明申请

US20100305527A1 CATHETER PRODUCT PACKAGE AND METHOD OF FORMING SAME 有权
公开(公告)号：US20100305527A1
公开(公告)日：2010-12-02
申请号：US12852959
申请日：2010-08-09
申请人： Michael Murray , Kai Jorgensen
发明人： Michael Murray , Kai Jorgensen
IPC分类号： A61B19/02 , A61F5/44
CPC分类号： B65D51/00 , A61M25/002 , A61M25/0111
摘要： A catheter product package and method of forming same in which the package comprises a sheet material wrapped about the catheter product to form a package for the catheter product. The catheter product extends generally longitudinally within the package, and the sheet material extends from a point beyond the proximal end to a point beyond the distal end of the catheter product. The sheet material of the package is wrapped about the catheter product in a manner defining confronting proximal end edges, confronting distal end edges, and confronting side edges. The confronting proximal end edges, distal end edges and side edges of the sheet material are joined by a seal after the sheet material is wrapped about the catheter product to define a sealed cavity. The sheet material has a tear strip affixed to it which causes the sheet material to tear along the tear strip to thereby cause the package to open along an intended opening line. A method of forming a package for a catheter product comprises the steps of providing a sheet material for the package and placing the catheter product on the sheet material. It also includes affixing a tear strip to the sheet material and wrapping the sheet material around the catheter product. Further, the method includes the step of sealing the sheet material to form a sealed cavity with the catheter product being disposed within the sealed cavity.

9. 发明申请

US20100153793A1 APPARATUS, METHODS, AND SYSTEM OF NAND DEFECT MANAGEMENT 有权
标题翻译： NAND缺陷管理的设备，方法和系统
公开(公告)号：US20100153793A1
公开(公告)日：2010-06-17
申请号：US12705916
申请日：2010-02-15
申请人： Michael Murray
发明人： Michael Murray
IPC分类号： G06F12/00 , G11C29/08 , G06F11/26 , G06F12/06
CPC分类号： G11C29/04 , G06F12/0246 , G06F2212/7201 , G11C29/08 , G11C29/76
摘要： Various embodiments comprise apparatus, methods, and systems including method comprising searching for a group address among a plurality of group addresses in a mapping table, and if a match is found, performing a memory operation on a first plurality of memory blocks indicated by the mapping table, and if a match is not found, performing a memory operation on a second plurality of memory blocks, the second plurality of memory blocks having the group address.
摘要翻译：各种实施例包括装置，方法和系统，包括以下方法：包括在映射表中的多个组地址之中搜索组地址，并且如果找到匹配，则对由映射指示的第一多个存储块执行存储器操作表，并且如果没有找到匹配，则对第二多个存储块执行存储器操作，所述第二多个存储块具有组地址。

10. 发明授权

US07545682B2 Erase block data splitting 有权
公开(公告)号：US07545682B2
公开(公告)日：2009-06-09
申请号：US11489321
申请日：2006-07-19
申请人： David Eggleston , Anthony Moschopoulos , Michael Murray , Brady Keays
发明人： David Eggleston , Anthony Moschopoulos , Michael Murray , Brady Keays
IPC分类号： G11C11/34
CPC分类号： G06F11/1008 , G06F11/1068 , G11C16/16
摘要： A Flash memory device, system, and data handling routine is detailed with a distributed erase block sector user/overhead data scheme that splits the user data and overhead data and stores them in differing associated erase blocks. The erase blocks of the Flash memory are arranged into associated erase block pairs in “super blocks” such that when user data is written to/read from the user data area of a sector of an erase block of the super block pair, the overhead data is written to/read from the overhead data area of a sector of the other associated erase block. This data splitting enhances fault tolerance and reliability of the Flash memory device.

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