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1. 发明授权

US07199450B2 Materials and method to seal vias in silicon substrates 有权
标题翻译：在硅衬底中密封通孔的材料和方法
公开(公告)号：US07199450B2
公开(公告)日：2007-04-03
申请号：US10908480
申请日：2005-05-13
申请人： Jon A. Casey , Michael Berger , Leena P. Buchwalter , Donald F. Canaperi , Raymond R. Horton , Anurag Jain , Eric D. Perfecto , James A. Tornello
发明人： Jon A. Casey , Michael Berger , Leena P. Buchwalter , Donald F. Canaperi , Raymond R. Horton , Anurag Jain , Eric D. Perfecto , James A. Tornello
IPC分类号： H01L29/06 , H01L23/58
CPC分类号： H01L23/147 , H01L21/486 , H01L21/76898 , H01L23/481 , H01L23/49827 , H01L2924/0002 , H01L2924/00
摘要： Sealing a via using a soventless, low viscosity, high temperature stable polymer or a high solids content polymer solution of low viscosity, where the polymeric material is impregnated within the via at an elevated temperature. A supply chamber is introduced to administer the polymeric material at an elevated temperature, typically at a temperature high enough to liquefy the polymeric material. The polymeric material is introduced through heated supply lines under force from a pump, piston, or a vacuum held within said supply chamber.
摘要翻译：使用无粘性，低粘度，高温稳定的聚合物或低粘度的高固含量聚合物溶液密封通孔，其中聚合物材料在高温下浸渍在通孔内。引入供应室以在升高的温度下施用聚合物材料，通常在高至足以液化聚合物材料的温度下。聚合物材料通过来自泵，活塞或保持在所述供应室内的真空的力的加热供应管线引入。

2. 发明授权

US08493746B2 Additives for grain fragmentation in Pb-free Sn-based solder 有权
标题翻译：在无铅锡基焊料中颗粒破碎的添加剂
公开(公告)号：US08493746B2
公开(公告)日：2013-07-23
申请号：US12704592
申请日：2010-02-12
申请人： Charles L. Arvin , Alexandre Blander , Peter J. Brofman , Donald W. Henderson , Gareth G. Hougham , Hsichang Liu , Eric D. Perfecto , Srinivasa S. N. Reddy , Krystyna W. Semkow , Kamalesh K. Srivastava , Brian R. Sundlof , Julien Sylvestre , Renee L. Weisman
发明人： Charles L. Arvin , Alexandre Blander , Peter J. Brofman , Donald W. Henderson , Gareth G. Hougham , Hsichang Liu , Eric D. Perfecto , Srinivasa S. N. Reddy , Krystyna W. Semkow , Kamalesh K. Srivastava , Brian R. Sundlof , Julien Sylvestre , Renee L. Weisman
IPC分类号： H05K7/00 , H05K1/03 , H05K1/11 , H05K7/10 , H01L23/48
CPC分类号： H01B1/02 , B23K35/0244 , B23K35/262 , B23K35/36 , B23K35/3602 , B82Y30/00 , C22C13/00 , H01B13/00 , H01L23/49866 , H01L2924/0002 , H05K3/3436 , H05K3/3463 , H05K2201/0209 , H05K2201/0257 , Y10T29/49117 , H01L2924/00
摘要： In one embodiment of the present invention, inert nano-sized particles having dimensions from 1 nm to 1,000 nm are added into a solder ball. The inert nano-sized particles may comprise metal oxides, metal nitrides, metal carbides, metal borides, etc. The inert nano-sized particles may be a single compound, or may be a metallic material having a coating of a different material. In another embodiment of the present invention, a small quantity of at least one elemental metal that forms stable high melting intermetallic compound with tin is added to a solder ball. The added at least one elemental metal forms precipitates of intermetallic compounds with tin, which are dispersed as fine particles in the solder.
摘要翻译：在本发明的一个实施方案中，将尺寸为1nm至1000nm的惰性纳米尺寸颗粒加入到焊球中。惰性纳米尺寸颗粒可以包括金属氧化物，金属氮化物，金属碳化物，金属硼化物等。惰性纳米尺寸颗粒可以是单一化合物，或者可以是具有不同材料的涂层的金属材料。在本发明的另一个实施方案中，将少量与锡形成稳定的高熔点金属间化合物的元素金属添加到焊料球中。添加的至少一种元素金属与锡形成金属间化合物的沉淀物，其作为细颗粒分散在焊料中。

3. 发明申请

US20110063815A1 Robust FBEOL and UBM Structure of C4 Interconnects 有权
标题翻译： C4互连的稳健FBEOL和UBM结构
公开(公告)号：US20110063815A1
公开(公告)日：2011-03-17
申请号：US12560769
申请日：2009-09-16
申请人： Minhua Lu , Eric D. Perfecto , David L. Questad , Sudipta K. Ray
发明人： Minhua Lu , Eric D. Perfecto , David L. Questad , Sudipta K. Ray
IPC分类号： H05K1/14 , H01R43/00
CPC分类号： H01L24/05 , H01L24/13 , H01L2224/0231 , H01L2224/0233 , H01L2224/0401 , H01L2224/05082 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/13022 , H01L2224/1308 , H01L2224/13082 , H01L2224/131 , H01L2224/13147 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01076 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/1461 , Y10T29/49117 , H01L2924/00014 , H01L2224/13099 , H01L2924/00
摘要： A microcircuit article of manufacture comprises an electrical conductor electrically connected to both a first microcircuit element at a site comprising a first connector site having a first connector site axis and a second microcircuit element at a site comprising a second connector site having a second connector site axis. The first microcircuit element and the second microcircuit element are separated by and operatively associated with a layer comprising a first electrical insulator, whereas the conductor and the first microcircuit element are separated by and operatively associated with a layer comprising a second electrical insulator. At least one of the first electrical insulator layer and the second electrical insulator layer comprise a polymeric electrical insulator. In another embodiment, both electrical insulator layers comprise polymeric insulator layers. The microcircuit includes a UBM and solder connection to a FBEOL via opening. Sufficiently separating the first connector site axis and the second connector site axis so they are not concentric decouples the UBM and solder connection to the FBEOL via opening to substantially eliminate or minimize inter alia, electromigration and the white bump problem typical of lead free solders employed in C4 systems. A process comprises manufacturing this type of microcircuit article.
摘要翻译：微电路制品包括电连接到第一微电路元件的电导体，该第一微电路元件包括具有第一连接器位置轴线的第一连接器位置和位于包括具有第二连接器位置轴线的第二连接器位置的第二微电路元件。第一微电路元件和第二微电路元件由包括第一电绝缘体的层分离并且可操作地相关联，而导体和第一微电路元件由包括第二电绝缘体的层分开并且可操作地与包含第二电绝缘体的层相连。第一电绝缘体层和第二电绝缘体层中的至少一个包括聚合物电绝缘体。在另一个实施例中，两个电绝缘体层包括聚合物绝缘体层。微电路包括UBM和通过开口焊接到FBEOL的焊接。足够地分离第一连接器位置轴和第二连接器位置轴线，使得它们不使UBM和FBEOL通过开口的焊接连接同步解耦，以基本上消除或最小化电迁移和典型的无铅焊料的白色凸起问题 C4系统。一种方法包括制造这种类型的微电路制品。

4. 发明授权

US06183588B2 Process for transferring a thin-film structure to a substrate 失效
标题翻译：将薄膜结构转印到基板的方法
公开(公告)号：US06183588B2
公开(公告)日：2001-02-06
申请号：US09460488
申请日：1999-12-14
申请人： Kimberley A. Kelly , Ashwani K. Malhotra , Eric D. Perfecto , Roy Yu
发明人： Kimberley A. Kelly , Ashwani K. Malhotra , Eric D. Perfecto , Roy Yu
IPC分类号： B32B3100
CPC分类号： B32B43/00 , B32B2310/0843 , B32B2311/00 , H01L21/6835 , H01L2221/68345 , H01L2221/68359 , H01L2221/68363 , H01L2924/3025 , H05K3/007 , H05K3/025 , H05K3/28 , H05K3/4614 , H05K3/4623 , H05K3/467 , H05K2201/09527 , H05K2201/10666 , H05K2203/016 , H05K2203/107 , Y10S156/922 , Y10S438/94 , Y10S438/974 , Y10S438/977 , Y10T156/11 , Y10T156/1158 , Y10T428/12528 , Y10T428/12583
摘要： A process for fabricating and releasing a thin-film structure from a primary carrier for further processing. The thin-film structure is built on a metal interconnect disposed on a dielectric layer which, in turn, is deposited on a primary carrier. The thin-film structure and metal interconnect are released from the dielectric layer and primary carrier along a release interface defined between the metal interconnect and the dielectric film. Release is accomplished by disturbing the interface, either by laser ablation or dicing. The process of the present invention has at least three, specific applications: (1) the thin-film structure and metal interconnect can be released to yield a free-standing film; (2) the thin-film structure and metal interconnect can be laminated onto a permanent substrate (when building top-side down structures) and then released; and (3) the thin-film structure can be transferred to a secondary temporary carrier (when building top-side up structures) for further processing and testing, then transferred to a permanent substrate before releasing the thin-film structure and metal interconnect.
摘要翻译：用于从主载体制造和释放薄膜结构以进一步处理的工艺。薄膜结构建立在设置在电介质层上的金属互连上，其又沉积在主载体上。薄膜结构和金属互连通过限定在金属互连和电介质膜之间的释放界面从电介质层和初级载体释放。通过激光烧蚀或切割来干扰界面来实现释放。本发明的方法具有至少三个具体应用：（1）可以释放薄膜结构和金属互连以产生独立的膜; （2）薄膜结构和金属互连可以层压在永久性基板上（当构建顶部向下结构时）然后释放; （3）可以将薄膜结构转移到二次临时载体（当构建顶侧上部结构）进行进一步的加工和测试时，在释放薄膜结构和金属互连之前转移到永久基板。

5. 发明授权

US6083375A Process for producing corrosion-resistant terminal metal pads for thin film packages 失效
标题翻译：用于制造薄膜封装的耐腐蚀端子金属焊盘的工艺
公开(公告)号：US6083375A
公开(公告)日：2000-07-04
申请号：US184169
申请日：1998-11-02
申请人： Tien-Jen Cheng , Ajay P. Giri , Ashwani K. Malhotra , John R. Pennacchia , Eric D. Perfecto , Roy Yu
发明人： Tien-Jen Cheng , Ajay P. Giri , Ashwani K. Malhotra , John R. Pennacchia , Eric D. Perfecto , Roy Yu
IPC分类号： H01L21/60 , C25D7/12 , H01L21/48 , H05K3/40 , C25D5/02 , C23C28/02 , C25D5/10 , C25D5/12
CPC分类号： H01L21/4853 , C25D7/123 , H01L24/16 , H05K3/4007 , Y10S428/929 , Y10S428/935 , Y10T428/12847 , Y10T428/12875 , Y10T428/12889
摘要： A process for producing a terminal metal pad structure electrically interconnecting a package and other components. More particularly, the invention encompasses a process for producing a plurality of corrosion-resistant terminal metal pads. Each pad includes a base pad containing copper which is encapsulated within a series of successively electroplated metal encapsulating films to produce a corrosion-resistant terminal metal pad.
摘要翻译：一种用于制造电连接封装和其它部件的端子金属焊盘结构的方法。更具体地，本发明包括用于制造多个耐腐蚀端子金属焊盘的方法。每个焊盘包括一个包含铜的基座，其被封装在一系列连续电镀的金属封装膜中以产生耐腐蚀的端子金属焊盘。

6. 发明授权

US5549808A Method for forming capped copper electrical interconnects 失效
标题翻译：形成封盖铜电互连的方法
公开(公告)号：US5549808A
公开(公告)日：1996-08-27
申请号：US440413
申请日：1995-05-12
申请人： Mukta S. Farooq , Suryanarayana Kaja , Eric D. Perfecto , George E. White
发明人： Mukta S. Farooq , Suryanarayana Kaja , Eric D. Perfecto , George E. White
IPC分类号： H01L21/768 , H05K1/03 , H05K3/06 , H05K3/10 , H05K3/38 , C25D5/02 , H01L21/288
CPC分类号： H05K3/108 , H01L21/76886 , H05K1/0306 , H05K2203/0597 , H05K2203/1105 , H05K3/062 , H05K3/388 , Y10S205/917
摘要： The present invention relates generally to a new structure and method for capped copper electrical interconnects. More particularly, the invention encompasses a novel structure in which one or more of the copper electrical interconnects within a semiconductor substrate are capped to obtain a robust electrical interconnect structure. A method for obtaining such capped copper electrical interconnect structure is also disclosed. These capped interconnects can be a single layer or multi-layer structures. Similarly, the interconnect structure that is being capped can itself be composed of single or multi-layered material.
摘要翻译：本发明一般涉及一种用于封盖铜电互连的新结构和方法。更具体地，本发明包括一种新颖的结构，其中半导体衬底内的一个或多个铜电互连被封盖以获得坚固的电互连结构。还公开了一种用于获得这种封盖铜电互连结构的方法。这些封装的互连可以是单层或多层结构。类似地，被封装的互连结构本身可以由单层或多层材料组成。

7. 发明授权

US08466543B2 Three dimensional stacked package structure 失效
标题翻译：三维堆叠包装结构
公开(公告)号：US08466543B2
公开(公告)日：2013-06-18
申请号：US12789316
申请日：2010-05-27
申请人： Thomas J. Fleischman , Eric D. Perfecto , Sudipta K. Ray
发明人： Thomas J. Fleischman , Eric D. Perfecto , Sudipta K. Ray
IPC分类号： H01L23/02 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L25/0657 , H01L23/49811 , H01L23/49827 , H01L24/04 , H01L24/05 , H01L24/06 , H01L24/14 , H01L24/16 , H01L25/0652 , H01L25/18 , H01L2224/0401 , H01L2224/0557 , H01L2224/06051 , H01L2224/06135 , H01L2224/06136 , H01L2224/06177 , H01L2224/06181 , H01L2224/1308 , H01L2224/13082 , H01L2224/131 , H01L2224/13111 , H01L2224/13116 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/14051 , H01L2224/14181 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2224/81801 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06558 , H01L2225/06572 , H01L2225/06586 , H01L2924/00013 , H01L2924/0002 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01075 , H01L2924/01077 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H01L2924/00014 , H01L2924/01046 , H01L2924/01028 , H01L2224/13099 , H01L2224/05552 , H01L2924/00
摘要： An apparatus, system, and method are disclosed for connecting integrated circuit devices. A plurality of primary electrically conductive contacts and a plurality of primary electrically conductive pillars are electrically coupled to a primary integrated circuit device. The plurality of primary electrically conductive contacts form a pattern corresponding to secondary electrically conductive contacts disposed on one or more secondary integrated circuit devices. The plurality of primary electrically conductive pillars extends away from the primary integrated circuit device. The plurality of primary electrically conductive pillars forms a pattern that corresponds to substrate electrically conductive contacts that are disposed on a substrate. The plurality of primary electrically conductive pillars and associated connecting material provide a standoff height between the primary integrated circuit device and the substrate that is greater than or equal to a height of the one or more secondary integrated circuit devices.
摘要翻译：公开了用于连接集成电路器件的装置，系统和方法。多个初级导电触点和多个初级导电柱电耦合到初级集成电路器件。多个初级导电触点形成对应于设置在一个或多个次级集成电路器件上的次级导电触点的图案。多个主导电支柱远离主集成电路装置延伸。多个主导电柱形成对应于设置在基板上的基板导电触点的图案。多个初级导电柱和相关联的连接材料提供主集成电路器件和衬底之间的间隔高度，其大于或等于一个或多个次级集成电路器件的高度。

8. 发明申请

US20120217287A1 FLIP CHIP ASSEMBLY METHOD EMPLOYING POST-CONTACT DIFFERENTIAL HEATING 失效
标题翻译：使用后接触差分加热的片状芯片组装方法
公开(公告)号：US20120217287A1
公开(公告)日：2012-08-30
申请号：US13036086
申请日：2011-02-28
申请人： Rajneesh Kumar , Jae-Woong Nah , Eric D. Perfecto
发明人： Rajneesh Kumar , Jae-Woong Nah , Eric D. Perfecto
IPC分类号： B23K31/02 , B23K1/20
CPC分类号： B23K1/0016
摘要： A first substrate mounted to a bonder head and a second substrate mounted to a base plate are held at different elevated temperatures at the time of bonding that provide a substantially matched thermal expansion between the second substrate and the first substrate relative to room temperature. Further, the temperature of the solder material portions and the second substrate is raised at least up to the melting temperature after contact. The distance between the first substrate and the second substrate can be modulated to enhance the integrity of solder joints. Once the distance is at an optimum, the bonder head is detached, and the bonded structure is allowed to cool to form a bonded flip chip structure. Alternately, the bonder head can control the cooling rate of solder joints by being attached to the chip during cooling step.
摘要翻译：安装到接合头的第一衬底和安装到基板的第二衬底在接合时被保持在不同的升高的温度，从而相对于室温在第二衬底和第一衬底之间提供基本匹配的热膨胀。此外，焊接材料部分和第二基板的温度至少升高到接触后的熔融温度。第一基板和第二基板之间的距离可被调制以增强焊点的完整性。一旦该距离处于最佳状态，就将分离头拆下，并使粘结结构冷却以形成结合的倒装芯片结构。或者，焊接头可以在冷却步骤期间通过附接到芯片来控制焊点的冷却速度。

9. 发明申请

US20100200271A1 ADDITIVES FOR GRAIN FRAGMENTATION IN Pb-FREE Sn-BASED SOLDER 有权
标题翻译：无铅锡基焊锡颗粒分散添加剂
公开(公告)号：US20100200271A1
公开(公告)日：2010-08-12
申请号：US12704592
申请日：2010-02-12
申请人： Charles L. Arvin , Alexandre Blander , Peter J. Brofman , Donald W. Henderson , Gareth G. Hougham , Hsichang Liu , Eric D. Perfecto , Srinivasa S.N. Reddy , Krystyna W. Semkow , Kamalesh K. Srivastava , Brian R. Sundlof , Julien Sylvestre , Renee L. Weisman
发明人： Charles L. Arvin , Alexandre Blander , Peter J. Brofman , Donald W. Henderson , Gareth G. Hougham , Hsichang Liu , Eric D. Perfecto , Srinivasa S.N. Reddy , Krystyna W. Semkow , Kamalesh K. Srivastava , Brian R. Sundlof , Julien Sylvestre , Renee L. Weisman
IPC分类号： H01B5/00 , H01R43/00
CPC分类号： H01B1/02 , B23K35/0244 , B23K35/262 , B23K35/36 , B23K35/3602 , B82Y30/00 , C22C13/00 , H01B13/00 , H01L23/49866 , H01L2924/0002 , H05K3/3436 , H05K3/3463 , H05K2201/0209 , H05K2201/0257 , Y10T29/49117 , H01L2924/00
摘要： In one embodiment of the present invention, inert nano-sized particles having dimensions from 1 nm to 1,000 nm are added into a solder ball. The inert nano-sized particles may comprise metal oxides, metal nitrides, metal carbides, metal borides, etc. The inert nano-sized particles may be a single compound, or may be a metallic material having a coating of a different material. In another embodiment of the present invention, a small quantity of at least one elemental metal that forms stable high melting intermetallic compound with tin is added to a solder ball. The added at least one elemental metal forms precipitates of intermetallic compounds with tin, which are dispersed as fine particles in the solder.
摘要翻译：在本发明的一个实施方案中，将尺寸为1nm至1000nm的惰性纳米尺寸颗粒加入到焊球中。惰性纳米尺寸颗粒可以包括金属氧化物，金属氮化物，金属碳化物，金属硼化物等。惰性纳米尺寸颗粒可以是单一化合物，或者可以是具有不同材料的涂层的金属材料。在本发明的另一个实施方案中，将少量与锡形成稳定的高熔点金属间化合物的元素金属添加到焊料球中。添加的至少一种元素金属与锡形成金属间化合物的沉淀物，其作为细颗粒分散在焊料中。

10. 发明授权

US5545927A Capped copper electrical interconnects 失效
公开(公告)号：US5545927A
公开(公告)日：1996-08-13
申请号：US440414
申请日：1995-05-12
申请人： Mukta S. Farooq , Suryanarayana Kaja , Eric D. Perfecto , George E. White
发明人： Mukta S. Farooq , Suryanarayana Kaja , Eric D. Perfecto , George E. White
IPC分类号： H01L23/498 , H01L23/532 , H05K1/03 , H05K3/06 , H05K3/10 , H05K3/38 , H05K3/46 , H01L23/48
CPC分类号： H05K3/108 , H01L23/498 , H01L23/49866 , H01L23/53228 , H01L2924/0002 , H01L2924/09701 , H05K1/0306 , H05K2203/0597 , H05K2203/1105 , H05K3/062 , H05K3/388 , H05K3/4644
摘要： The present invention relates generally to a new structure and method for capped copper electrical interconnects. More particularly, the invention encompasses a novel structure in which one or more of the copper electrical interconnects within a semiconductor substrate are capped to obtain a robust electrical interconnect structure. A method for obtaining such capped copper electrical interconnect structure is also disclosed. These capped interconnects can be a single layer or multi-layer structures. Similarly, the interconnect structure that is being capped can itself be composed of single or multi-layered material.

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