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    • 3. 发明授权
    • Method for post forming a rounded insertion end of a tampon pledget of
an open-ended applicator
    • 用于后端形成开口施用器的棉塞的圆形插入端的方法
    • US5634248A
    • 1997-06-03
    • US502589
    • 1995-07-14
    • Thomas C. McNelisJamshid RejaiRichard A. Weber
    • Thomas C. McNelisJamshid RejaiRichard A. Weber
    • A61F13/20A61F13/26D04H1/06
    • A61F13/2085A61F13/2051A61F13/26
    • There is provided a method for forming a round, hemispherical shape at the forward insertion end of a tampon pledget after the pledget has been assembled within a tampon applicator. The pledget is assembled within the applicator so that a portion of its fibers is exposed at an open insertion end of the applicator. After assembly, an insertion end formation tool is applied to the exposed fibers to form a depression in the middle of the insertion end and a full periphery cushion that flares peripherally outward from the depression. The insertion end formation tool has a reverse-donut shaped curvature with a central projection or spike. The central spike reduces the axial force necessary to form the full periphery cushion by radially displacing the fibers in the central location or middle of the insertion end of the pledget. With the insertion end formed in accordance with the method of present invention, the full periphery cushion provides a rounded, forward or insertion end to facilitate an application of the tampon for its intended use.
    • 提供了一种在棉签组装在卫生棉条敷料器中之后在棉塞的前部插入端处形成圆形半球形的方法。 将毛细管组装在施用器内,使得其一部分纤维在施用器的开放插入端露出。 在组装之后,将插入端形成工具施加到暴露的纤维上以在插入端的中间形成凹陷,以及从凹部向外周向向外张开的全周围垫。 插入端形成工具具有具有中心突起或尖峰的反向环形曲率。 中心钉通过径向移位纤维在插入端的插入端的中心位置或中间而减小形成整个周边垫所需的轴向力。 随着根据本发明的方法形成的插入端,全周边衬垫提供圆形的,向前的或插入的端部,以促进卫生棉条应用于其预期用途。
    • 9. 发明授权
    • Fabrication of dielectrically isolated fine line semiconductor
transducers and apparatus
    • 介质隔离的细线半导体传感器和设备的制造
    • US4672354A
    • 1987-06-09
    • US804761
    • 1985-12-05
    • Anthony D. KurtzTimothy A. NunnRichard A. Weber
    • Anthony D. KurtzTimothy A. NunnRichard A. Weber
    • G01L1/22G01L9/00H01L21/306B44C1/22G01B7/16H01C17/00
    • G01L1/2293G01L9/0042Y10S73/04Y10T29/42Y10T29/49103
    • There is disclosed apparatus and methods of fabricating a piezoresistive semiconductor structure for use in a transducer. According to one method, a layer of silicon dioxide is grown over the surface of a first semiconductor wafer which is designated as a carrier wafer. A layer of glas is then formed on the top surface of the carrier wafer over said layer of silicon dioxide. A second wafer has diffused therein a high conductivity semiconductor layer which is diffused on a top surface of a sacrificial semiconductor wafer. The first and second wafers are then bonded together by means of an electrostatic bond with the high conductivity layer of the sacrificial wafer facing the glass layer of the first wafer. After securing the wafers together, one may etch away the remaining portion of the sacrificial wafer to provide a high conductivity resistive layer which is secured to the glass layer of the first wafer and is patterned to form a resistive network using standard photolithographic making. In another embodiment, the sacrificial wafer is processed by means of a high conductivity diffusion procedure whereby a resistive line pattern is formed in the second wafer. After diffusion, the second wafer is etched so that the high conductivity pattern projects from the top surface. This top surface consisting of the projected high conductivity resistive pattern is then bonded to the glass layer of the second wafer. After bonding the two wafers together, the unwanted N-type regions of the sacrificial wafer are etched away using a conductivity selective etch to form the resistive pattern.
    • 公开了制造用于换能器的压阻半导体结构的装置和方法。 根据一种方法,在指定为载体晶片的第一半导体晶片的表面上生长二氧化硅层。 然后在载体晶片的顶表面上形成一层玻璃,该层在二氧化硅层上。 第二晶片在其中扩散了在牺牲半导体晶片的顶表面上扩散的高导电性半导体层。 第一和第二晶片然后通过与第一晶片的玻璃层的牺牲晶片的高电导率层的静电键结合在一起。 在将晶片固定在一起之后,可以蚀刻掉牺牲晶片的剩余部分,以提供固定到第一晶片的玻璃层的高导电性电阻层,并使用标准光刻制作来形成电阻网络。 在另一个实施例中,牺牲晶片通过高电导率扩散程序进行处理,由此在第二晶片中形成电阻线图案。 在扩散之后,蚀刻第二晶片,使得高导电性图案从顶表面突出。 然后将由投影的高导电性电阻图形组成的顶表面结合到第二晶片的玻璃层。 在将两个晶片结合在一起之后,使用电导率选择性蚀刻将牺牲晶片的不想要的N型区域蚀刻掉以形成电阻图案。