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    • 6. 发明授权
    • Multiport memory architecture with direct data flow
    • 具有直接数据流的多端口存储器架构
    • US06434674B1
    • 2002-08-13
    • US09542585
    • 2000-04-04
    • Mark DeWildeStephen Stone
    • Mark DeWildeStephen Stone
    • G06F1316
    • G06F13/1673G06F13/1678
    • The present invention provides a high speed, multi-ported, direct data flow memory architecture that employs memory width and speed greater than system bus width and speed to allow shallow burst depth and reduce other-port latencies, while maintaining multi-port throughput. The inventive system has a data storage device (SDRAM) and a multiplexer connected to the SDRAM. Two or more interfaces or ports are provided with data sourcing controllers respectively connected to the interfaces. A communications bus connects the SDRAM to the data sourcing controllers for facilitating data communications. A FIFO buffer memory is located between the multiplexer and the data sourcing controllers. The need for retries is eliminated and host bus widths are matched to memory data width. Read-ahead algorithms are provided that adapt the larger system bus burst sizes to the smaller memory burst sizes with the ability to cancel unneeded advance requests for data. The total memory bandwidth is greater than that of the sum of the ports, so that the small memory burst size inefficiency does not reduce throughput below target levels. Write data is selectively masked to eliminate the need for read-modify-write cycles. Reads and writes can begin and end on arbitrary byte addresses, regardless of memory or bus widths.
    • 本发明提供了一种高速,多端口的直接数据流存储器架构,其采用大于系统总线宽度和速度的存储器宽度和速度,以允许浅突发深度并减少其他端口延迟,同时保持多端口吞吐量。 本发明的系统具有连接到SDRAM的数据存储设备(SDRAM)和多路复用器。 两个或多个接口或端口提供有分别连接到接口的数据源控制器。 通信总线将SDRAM连接到数据采集控制器,以便于数据通信。 FIFO缓冲存储器位于多路复用器和数据采集控制器之间。 消除对重试的需要,并将主机总线宽度与存储器数据宽度相匹配。 提供了预读算法,其将较大的系统总线脉冲串大小适应于较小的存储器突发大小,具有取消不需要的数据提前请求的能力。 总内存带宽大于端口总和的大小,因此小内存突发大小无效率不会将吞吐量降低到目标级别以下。 选择性地屏蔽写入数据,以消除对读 - 修改 - 写周期的需要。 无论存储器或总线宽度如何,读写都可以在任意字节地址开始和结束。
    • 7. 发明授权
    • Dynamic adjustment of multiple sequential burst data transfers
    • 多次连续突发数据传输的动态调整
    • US06571302B1
    • 2003-05-27
    • US10172405
    • 2002-06-14
    • Mark DeWildeStephen Stone
    • Mark DeWildeStephen Stone
    • G06F1332
    • G06F13/1673G06F13/1678
    • The present invention provides a high speed, multi-ported, direct data flow memory architecture that employs memory width and speed greater than system bus width and speed to allow shallow burst depth and reduce other-port latencies, while maintaining multi-port throughput. The inventive system has a data storage device (SDRAM) and a multiplexer connected to the SDRAM. Two or more interfaces or ports are provided with data sourcing controllers respectively connected to the interfaces. A communications bus connects the SDRAM to the data sourcing controllers for facilitating data communications. A FIFO buffer memory is located between the multiplexer and the data sourcing controllers. The need for retries is eliminated and host bus widths are matched to memory data width. Read-ahead algorithms are provided that adapt the larger system bus burst sizes to the smaller memory burst sizes with the ability to cancel unneeded advance requests for data. The total memory bandwidth is greater than that of the sum of the ports, so that the small memory burst size inefficiency does not reduce throughput below target levels. Write data is selectively masked to eliminate the need for read-modify-write cycles. Reads and writes can begin and end on arbitrary byte addresses, regardless of memory or bus widths.
    • 本发明提供了一种高速,多端口的直接数据流存储器架构,其采用大于系统总线宽度和速度的存储器宽度和速度,以允许浅突发深度并减少其他端口延迟,同时保持多端口吞吐量。 本发明的系统具有连接到SDRAM的数据存储设备(SDRAM)和多路复用器。 两个或多个接口或端口提供有分别连接到接口的数据源控制器。 通信总线将SDRAM连接到数据采集控制器,以便于数据通信。 FIFO缓冲存储器位于多路复用器和数据采集控制器之间。 消除对重试的需要,并将主机总线宽度与存储器数据宽度相匹配。 提供了预读算法,其将较大的系统总线脉冲串大小适应于较小的存储器突发大小,具有取消不需要的数据提前请求的能力。 总内存带宽大于端口总和的大小,因此小内存突发大小无效率不会将吞吐量降低到目标级别以下。 选择性地屏蔽写入数据,以消除对读 - 修改 - 写周期的需要。 无论存储器或总线宽度如何,读写都可以在任意字节地址开始和结束。