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1. 发明申请

US20050079889A1 Cellular modem processing 有权
标题翻译：蜂窝式调制解调器处理
公开(公告)号：US20050079889A1
公开(公告)日：2005-04-14
申请号：US10682746
申请日：2003-10-09
申请人： John Vaglica , Christopher Chun , Jose Corleto-Mena , Arnaldo Cruz , Jianping Tao , Mieu Vu , Mark Elledge , Charbel Khawand , Arthur Goldberg , David Hayes
发明人： John Vaglica , Christopher Chun , Jose Corleto-Mena , Arnaldo Cruz , Jianping Tao , Mieu Vu , Mark Elledge , Charbel Khawand , Arthur Goldberg , David Hayes
IPC分类号： H04M11/00 , H04W84/08 , H04B1/38
CPC分类号： H04W84/08
摘要： A cellular mobile station including a modem processor and memory. The memory includes instructions for the modem processor to perform layer 1 processor operations, layer 2 processor operations, and layer 3 processor operations. The modem processor executes the instructions to perform processor operations for the cellular mobile station to communication data as per a cellular communications protocol. In one example, the mobile station includes different levels of memory to provide different deterministic access times
摘要翻译：包括调制解调器处理器和存储器的蜂窝移动站。存储器包括用于调制解调器处理器执行第1层处理器操作，第2层处理器操作和第3层处理器操作的指令。调制解调器处理器执行指令，以便根据蜂窝通信协议对蜂窝移动站执行通信数据的处理器操作。在一个示例中，移动站包括不同级别的存储器以提供不同的确定性访问时间

2. 发明申请

US20050215227A1 Method and apparatus for entering a low power mode 有权
标题翻译：用于进入低功率模式的方法和装置
公开(公告)号：US20050215227A1
公开(公告)日：2005-09-29
申请号：US10806498
申请日：2004-03-23
申请人： Mieu Vu , Christopher Chun , Arthur Goldberg , David Hayes , Charbel Khawand , Jianping Tao , John Vaglica
发明人： Mieu Vu , Christopher Chun , Arthur Goldberg , David Hayes , Charbel Khawand , Jianping Tao , John Vaglica
IPC分类号： H04B1/16 , H04B1/38
CPC分类号： H04W52/0277 , Y02D70/00
摘要： A method and apparatus for entering a low power mode is provided. In one embodiment, data processing system (10) has power control circuitry (52) which may be used to control power usage in data processing system (10). Power mode select circuitry (84) may be used to select a power mode. Depending upon the power mode selected, power control circuitry (52) may use a cascaded approach to selecting which portions of data processing system (10) will be powered down, and thus how deeply data processing system (10) will be powered down.
摘要翻译：提供一种用于进入低功率模式的方法和装置。在一个实施例中，数据处理系统（10）具有功率控制电路（52），其可用于控制数据处理系统（10）中的功率使用。电源模式选择电路（84）可用于选择电源模式。根据所选择的功率模式，功率控制电路（52）可以使用级联的方法来选择数据处理系统（10）的哪些部分将被掉电，并且因此数据处理系统（10）将被断电多深。

3. 发明申请

US20050068799A1 Integrated circuit power management for reducing leakage current in circuit arrays and method therefor 有权
公开(公告)号：US20050068799A1
公开(公告)日：2005-03-31
申请号：US10675005
申请日：2003-09-30
申请人： Ryan Bedwell , Christopher Chun , Qadeer Qureshi , John Vaglica
发明人： Ryan Bedwell , Christopher Chun , Qadeer Qureshi , John Vaglica
IPC分类号： G06F1/32 , G11C5/14 , G11C7/22 , G11C7/00 , G11C5/06
CPC分类号： G06F1/3275 , G06F1/3203 , G11C5/14 , G11C7/22 , G11C2207/2227 , Y02D10/14
摘要： Leakage current is eliminated in a memory array during a low power mode of a processing system having a processor that interfaces with the memory array. Because two power planes are created, the processor may continue executing instructions using a system memory while bypassing the memory array when the array is powered down. A switch selectively removes electrical connectivity to a supply voltage terminal in response to either processor-initiated control resulting from execution of an instruction or from a source originating in the system somewhere else than the processor. Upon restoration of power to the memory array, data may or may not need to be marked as unusable depending upon which of the two power planes supporting arrays to the memory array are located. Predetermined criteria may be used to control the timing of the restoration of power. Multiple arrays may be implemented to independently reduce leakage current.

4. 发明申请

US20050218952A1 State retention within a data processing system 有权
公开(公告)号：US20050218952A1
公开(公告)日：2005-10-06
申请号：US10818861
申请日：2004-04-06
申请人： Milind Padhye , Christopher Chun , Yuan Yuan , Sanjay Gupta
发明人： Milind Padhye , Christopher Chun , Yuan Yuan , Sanjay Gupta
IPC分类号： G11C5/14 , G11C11/00
CPC分类号： G11C5/147
摘要： Power consumption may be reduced through the use of power gating in which power is removed from circuit blocks or portions of circuit blocks in order to reduce leakage current. One embodiment uses a modified state retention flip-flop capable of retaining state when power is removed or partially removed from the circuit. Another embodiment uses a modified state retention buffer capable of retaining state when power is removed or partially removed from the circuit. The state retention flip-flop and buffer may be used to allow for state retention while still reducing leakage current. Also disclosed are various methods of reducing power and retaining state using, for example, the state retention flip-flops and buffers. For example, software, hardware, or a combination of software and hardware methods may be used to enter a deep sleep or idle mode while retaining state.

5. 发明申请

US20130227327A1 System and Method For Managing Electrical Current In A Portable Computing Device 有权
标题翻译：在便携式计算设备中管理电流的系统和方法
公开(公告)号：US20130227327A1
公开(公告)日：2013-08-29
申请号：US13428154
申请日：2012-03-23
申请人： Christopher Chun , Amy Derbyshire , Jon J. Anderson , Christopher Patrick , Todd Sutton , Eric Ian Mikuteit
发明人： Christopher Chun , Amy Derbyshire , Jon J. Anderson , Christopher Patrick , Todd Sutton , Eric Ian Mikuteit
IPC分类号： G06F11/30 , G06F1/26
CPC分类号： G06F11/3058 , G06F1/26 , G06F1/3212 , G06F1/324 , Y02D10/126 , Y02D10/174
摘要： An electrical current (“EC”) manager module may assign a plurality of hardware elements of the PCD to one of two groups. The EC manager module may monitor individual electrical current levels of one of the groups as well as calculate an instantaneous electrical current level for the PCD based on a current charge status for the PCD. The EC manager module may then adjust operation of at least one hardware element to keep operation of the PCD below the calculated instantaneous electrical current level for the PCD. The EC manager module may estimate an electrical current level for one of the groups based on requests issued to hardware elements. The EC manager module may also compare the calculated instantaneous electrical current level to the monitored electrical current level. The calculated instantaneous electrical current level may be compared to minimum current levels listed in a table.
摘要翻译：电流（“EC”）管理器模块可以将PCD的多个硬件元件分配给两个组中的一个。 EC管理器模块可以监视组中的一个的各个电流电平，并且基于PCD的当前充电状态来计算PCD的瞬时电流水平。 EC管理器模块然后可以调整至少一个硬件元件的操作，以将PCD的操作保持在PCD的计算出的瞬时电流水平以下。 EC管理器模块可以基于向硬件元件发出的请求来估计组中的一个的电流水平。 EC管理器模块还可以将所计算的瞬时电流水平与所监视的电流水平进行比较。计算出的瞬时电流水平可以与表中列出的最小电流水平进行比较。

6. 发明申请

US20090175393A1 METHOD AND DEVICE FOR FRAME SYNCHRONIZATION 有权
标题翻译：用于帧同步的方法和装置
公开(公告)号：US20090175393A1
公开(公告)日：2009-07-09
申请号：US11917111
申请日：2005-06-10
申请人： Michael Priel , Christopher Chun , Gordon P. Lee , Cor Voorwinden
发明人： Michael Priel , Christopher Chun , Gordon P. Lee , Cor Voorwinden
IPC分类号： H04L7/00
CPC分类号： G06F13/4291 , Y02D10/14 , Y02D10/151
摘要： A method for frame synchronization, the method includes providing a high frequency clock signal over a clock line during a transmission of information over a data line connected to a media access controller and to at least one component; characterized by defining a short synchronization period; processing at least one signal conveyed over the data line during the short synchronization period to determine a presence of a synchronization error; and maintaining at least the clock line in a low power mode when the data line is substantially idle.A device having frame synchronization capabilities, the device includes a clock signal provider and at least one component connected to a data line. The clock signal provider is adapted to provide a high frequency clock signal over a clock line during a transmission of information over the data line. The at least one component is adapted to process at least one signal conveyed over the data line during a short synchronization period to determine a presence of a synchronization error. The device is further adapted to maintain at least the clock line in a low power mode when the data line is substantially idle.
摘要翻译：一种用于帧同步的方法，所述方法包括在通过连接到媒体访问控制器的数据线和至少一个组件的信息传输期间在时钟线上提供高频时钟信号; 其特征在于定义短的同步周期; 处理在短同步周期期间通过数据线路传送的至少一个信号，以确定同步误差的存在; 以及当所述数据线基本为空闲时，至少将所述时钟线保持在低功率模式。具有帧同步能力的设备，该设备包括时钟信号提供器和连接到数据线的至少一个组件。时钟信号提供器适于在数据线上的信息传输期间通过时钟线提供高频时钟信号。所述至少一个组件适于在短同步周期期间处理在数据线上传送的至少一个信号，以确定同步误差的存在。该装置还适于在数据线基本上空闲时将至少时钟线保持在低功率模式。

7. 发明授权

US06753719B2 System and circuit for controlling well biasing and method thereof 有权
公开(公告)号：US06753719B2
公开(公告)日：2004-06-22
申请号：US10227893
申请日：2002-08-26
申请人： Gayathri A. Bhagavatheeswaran , Hong Tian , Christopher Chun
发明人： Gayathri A. Bhagavatheeswaran , Hong Tian , Christopher Chun
IPC分类号： H03K301
CPC分类号： H02M3/07 , H03K2217/0018
摘要： A well bias controller receives input from a sensor. The sensor indicates when a desired threshold condition, such as a temperature or current limit has been exceeded. Threshold conditions are chosen so that when the threshold condition is exceeded, the amount of current drawn by the well bias circuit and through the transistor exceeds the amount of leakage current that would otherwise occur in the device if a well bias circuit were not used. Whenever it is determined, based on the threshold condition, that the well bias circuit is using more current than a device would otherwise leak, the controller turns the well bias circuit off.

8. 发明申请

US20060255849A1 State retention power gating latch circuit 有权
标题翻译：状态保持电源门控锁存电路
公开(公告)号：US20060255849A1
公开(公告)日：2006-11-16
申请号：US11125462
申请日：2005-05-10
申请人： Christopher Chun
发明人： Christopher Chun
IPC分类号： H03L7/00
CPC分类号： H03K3/356008 , H03K3/012
摘要： A method of power gating a latch including detecting a state of the latch, detecting a power gate signal, providing power to the latch while the power gate signal is negated, and removing power from the latch when the power gate signal is asserted and the latch is in a predetermined state. The method may include any one or more of pulling a node of the latch to a selected state while the power gate signal is asserted to ensure that the latch powers up in the predetermined state, providing a signal indicative of the latch state and the power gate signal to respective inputs of a logic gate having an output indicative thereof, switching a supply voltage to a power input of the latch based on a state of the output of the logic gate, and closing a switch to pull a node of the latch low.
摘要翻译：一种锁存电源的方法，包括检测锁存器的状态，检测功率门信号，在功率门信号被否定时为锁存器供电，以及当功率门信号被断言时从锁存器去除功率，并且锁存器处于预定状态。该方法可以包括以下任何一个或多个：将锁存器的节点拉至选定状态，同时确定电源门信号以确保锁存器在预定状态下上电，提供指示锁存状态的信号和电源门信号到具有指示输出的逻辑门的相应输入，基于逻辑门的输出状态将电源电压切换到锁存器的电源输入，并且闭合开关以将锁存器的节点拉低。

9. 发明申请

US20050071693A1 Method and circuitry for controlling supply voltage in a data processing system 有权
标题翻译：用于控制数据处理系统中电源电压的方法和电路
公开(公告)号：US20050071693A1
公开(公告)日：2005-03-31
申请号：US10672161
申请日：2003-09-26
申请人： Christopher Chun , Wayne Ballantyne , Gordon Lee , Scott Tassi , Darren Weninger
发明人： Christopher Chun , Wayne Ballantyne , Gordon Lee , Scott Tassi , Darren Weninger
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/3237 , G06F1/3203 , G06F1/3287 , G06F1/3296 , Y02D10/128 , Y02D10/171 , Y02D10/172 , Y02D50/20
摘要： Supply voltages within a data processing system may be controlled by a voltage control module which can provide digital signals to a power management unit to cause changes in supply voltages without software intervention. For example, in one embodiment, a voltage control signal and a standby signal may be provided to control the supply voltages output by a voltage regulator within the power management unit. In one embodiment having multiple processors, a voltage control signal and a standby signal corresponding to each processor may be provided to the power management unit which has a voltage regulator supplying an independently controlled supply voltage to each processor. Alternatively, a voltage regulator, a voltage control signal, and a standby signal may be shared by multiple processors, where the voltage control module may ensure that the supply voltage is changed only when the change is appropriate for all processors sharing the same voltage regulator.
摘要翻译：数据处理系统内的电源电压可以由电压控制模块来控制，电压控制模块可以向电源管理单元提供数字信号，从而在没有软件干预的情况下引起电源电压的变化。例如，在一个实施例中，可以提供电压控制信号和待机信号以控制由电力管理单元内的电压调节器输出的电源电压。在具有多个处理器的一个实施例中，可以向功率管理单元提供对应于每个处理器的电压控制信号和待机信号，该电源管理单元具有向每个处理器提供独立控制的电源电压的电压调节器。或者，电压调节器，电压控制信号和备用信号可以由多个处理器共享，其中电压控制模块可以确保仅当变化适用于共享相同电压调节器的所有处理器时才改变电源电压。

10. 发明申请

US20050057296A1 Level shifter 有权
标题翻译：电平移位器
公开(公告)号：US20050057296A1
公开(公告)日：2005-03-17
申请号：US10660847
申请日：2003-09-12
申请人： Shivraj Dharne , Shahid Ali , Christopher Chun , Claude Moughanni
发明人： Shivraj Dharne , Shahid Ali , Christopher Chun , Claude Moughanni
IPC分类号： H03K3/356 , H03L5/00
CPC分类号： H03K3/356113
摘要： A level shifter for an integrated circuit. In one embodiment, the level shifter is a bi-directional level shifter with a signal terminal located in each voltage domain that can be utilized as input or output terminal. In some embodiments, the level shifter includes transistors for cutting off the flow of current between domain power supplies when the input terminals are at a particular state. In one embodiment, only one signal line of the level shifter crosses a domain boundary.
摘要翻译：集成电路的电平移位器。在一个实施例中，电平移位器是双向电平移位器，其中信号端子位于可用作输入或输出端子的每个电压域中。在一些实施例中，电平移位器包括用于在输入端处于特定状态时切断域电源之间的电流的晶体管。在一个实施例中，电平移位器中只有一条信号线与域边界交叉。

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