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    • 9. 发明授权
    • Dram with new I/O data path configuration
    • 引入新的I / O数据路径配置
    • US5966338A
    • 1999-10-12
    • US47304
    • 1998-03-24
    • Lawrence C. LiuMichael A. MurrayLi-Chun Li
    • Lawrence C. LiuMichael A. MurrayLi-Chun Li
    • G11C7/10G11C11/4096G11C7/02
    • G11C11/4096G11C7/1048G11C7/1051
    • In accordance with this invention, a DRAM with a staggered bitline sense amplifier configuration utilizes an I/O data path scheme which minimizes the time delay through the I/O data path. The DRAM includes a first and a second memory arrays wherein a first external sense amplifier receives on an input terminal a signal corresponding to the state of a memory cell selected from the first memory array via a first column decoding circuit. A second external sense amplifier receives on an input terminal a signal corresponding to the state of a memory cell selected form the second memory array via a second column decoding circuit. Each of the two external sense amplifiers has an output terminal which are shorted together. A tristate signal feeding another input terminal of each of the two external sense amplifiers is used to eliminate data contention on the shorted output terminals.
    • 根据本发明,具有交错位线读出放大器配置的DRAM利用I / O数据路径方案,其使通过I / O数据路径的时间延迟最小化。 DRAM包括第一和第二存储器阵列,其中第一外部读出放大器经由第一列解码电路在输入端子上接收对应于从第一存储器阵列选择的存储器单元的状态的信号。 第二外部读出放大器经由第二列解码电路在输入端子上接收对应于从第二存储器阵列选择的存储器单元的状态的信号。 两个外部读出放大器中的每一个具有一起短接的输出端子。 使用两个外部读出放大器中的每一个的另一个输入端子的三态信号来消除短路输出端子上的数据争用。
    • 10. 发明授权
    • Generation of signals from other signals that take time to develop on
power-up
    • 生成来自其他信号的信号,在上电时需要时间进行开发
    • US5907257A
    • 1999-05-25
    • US853291
    • 1997-05-09
    • Lawrence LiuMichael A. MurrayLi-Chun Li
    • Lawrence LiuMichael A. MurrayLi-Chun Li
    • G05F1/46G05F1/10
    • G05F1/468G05F1/465
    • A bias voltage generator generates the same bias voltage VBB for different external power supply voltages EVCC (for example, for EVCC=3.3V or 5.0V). During power-up, the charge pump that generates VBB is controlled by an enable signal ExtEn referenced to EVCC. Later an internal supply voltage IVCC becomes fully developed to a value independent from EVCC (for example, IVCC=3.0V), and the charge pump becomes controlled by an enable signal IntEn referenced to IVCC. This enable signal IntEn will cause VBB to reach its target value, for example, -1.5V. This target value is independent of EVCC. During power-up, when the charge pump is controlled by ExtEn, the bias voltage VBB is driven to an intermediate value (for example, -0.5V or -1V). This intermediate value depends on EVCC, but is below the target value in magnitude. The intermediate value reduces the likelihood of latch-up during power-up, but the intermediate value does not go beyond the target value thus does not create a significant pn-junction current leakage in semiconductor regions to which the bias voltage is applied.
    • 偏置电压发生器为不同的外部电源电压EVCC产生相同的偏置电压VBB(例如,对于EVCC = 3.3V或5.0V)。 在上电期间,产生VBB的电荷泵由参考EVCC的使能信号ExtEn控制。 之后,内部电源电压IVCC完全发展为独立于EVCC(例如,IVCC = 3.0V)的值,并且电荷泵由参考IVCC的使能信号IntEn控制。 该启用信号IntEn将使VBB达到其目标值,例如-1.5V。 该目标值与EVCC无关。 在上电期间,当电荷泵由ExtEn控制时,偏置电压VBB被驱动到中间值(例如,-0.5V或-1V)。 该中间值取决于EVCC,但是在大小上低于目标值。 中间值降低了在上电期间闭锁的可能性,但是中间值不超过目标值,因此在施加偏置电压的半导体区域中不会产生显着的pn结电流泄漏。