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1. 发明授权

US6040568A Multipurpose readout integrated circuit with in cell adaptive non-uniformity correction and enhanced dynamic range 失效
标题翻译：多通道读出集成电路，具有单元自适应非均匀性校正和增强的动态范围
公开(公告)号：US6040568A
公开(公告)日：2000-03-21
申请号：US073408
申请日：1998-05-06
申请人： John T. Caulfield , Richard H. Wyles , John D. Schlesselmann , Kevin L. Pettijohn
发明人： John T. Caulfield , Richard H. Wyles , John D. Schlesselmann , Kevin L. Pettijohn
IPC分类号： H04N5/33 , H04N5/365 , H04N5/378 , H01L25/00
CPC分类号： H04N5/365 , H04N5/33 , H01L2924/0002
摘要： An IR-FPA (10) having a plurality of radiation detectors (2a) and a multipurpose ROIC (2) is disclosed. The radiation detectors (2a) are organized as a two dimensional array. The multipurpose ROIC (2) includes a plurality of readout circuit unit cells, individual ones of which are coupled to individual radiation detectors (2a) for receiving electrical signals therefrom. Each of the readout circuit unit cells operates in one of a first mode to provide a corrected m frame averaged output signal (Vout.sub.THPF) or, a second mode to provide a subframed averaged output signal (Vout.sub.2). In the first operating mode, a high pass filtering circuit subtracts a low frequency charge pedestal from the electrical signal to form the corrected m frame averaged output (Vout.sub.THPF). Also disclosed is a method for operating an array of radiation detectors (2a) which includes the steps of: within a sampling period that defines a frame comprised of subframe periods, generating an electrical signal in individual ones of the radiation detectors, the electrical signals being generated in response to incident radiation; in a first operating mode, forming a high pass filtered output signal (Vout.sub.THPF) from electrical signals generated during at least one frame period; in a second operating mode, forming a subframe averaged output signal (Vout.sub.2) from electrical signals generated during a frame period; and reading out, in the first operating mode, the high pass filtered output signal (Vout.sub.THPF) or, in the second operating mode, the subframe averaged output signal (Vout.sub.2).
摘要翻译：公开了具有多个辐射检测器（2a）和多用途ROIC（2）的IR-FPA（10）。辐射检测器（2a）被组织为二维阵列。多用途ROIC（2）包括多个读出电路单位单元，其中各个耦合到各个辐射检测器（2a），用于从其接收电信号。每个读出电路单元以第一模式中的一个工作，以提供校正的m帧平均输出信号（VoutTHPF），或者提供次级平均输出信号（Vout2）的第二模式。在第一操作模式中，高通滤波电路从电信号中减去低频电荷基座，以形成校正后的m帧平均输出（VoutTHPF）。还公开了一种用于操作辐射检测器（2a）阵列的方法，其包括以下步骤：在定义由子帧周期组成的帧的采样周期内，在各个辐射检测器中产生电信号，电信号为响应入射辐射而产生的; 在第一操作模式中，从在至少一个帧周期期间产生的电信号形成高通滤波输出信号（VoutTHPF）; 在第二操作模式中，从在帧周期期间产生的电信号形成子帧平均输出信号（Vout2）; 并且在第一操作模式中读出高通滤波输出信号（VoutTHPF），或者在第二操作模式下读出子帧平均输出信号（Vout2）。

2. 发明授权

US5477173A Ultra low power gain circuit (UGC) 失效
标题翻译：超低功耗增益电路（UGC）
公开(公告)号：US5477173A
公开(公告)日：1995-12-19
申请号：US100648
申请日：1993-07-30
申请人： John D. Schlesselmann , Kevin L. Pettijohn , William H. Frye , Mary J. Hewitt
发明人： John D. Schlesselmann , Kevin L. Pettijohn , William H. Frye , Mary J. Hewitt
IPC分类号： H03K17/687 , H03K19/0185 , H03K3/353
CPC分类号： H03K19/01855 , H03K17/687
摘要： An ultra low power gain circuit (UGC) implements a unique operational mode of a source follower circuit, and enables programmable gains greater than unity. A MOSFET has a gate terminal coupled to an input capacitance (Cin). A potential at a drain of the MOSFET is clocked to enable charge to flow through the channel. This charge charges a capacitor (Cout) that is connected to a source of the MOSFET. After charging Cout, the drain potential is restored to an initial value, and the charge on Cout discharges back through the MOSFET until the source voltage is one threshold drop from the gate potential, at which time the MOSFET turns off. Cout then stops discharging, and the final voltage appearing on Cout is a function of the magnitude of the gate voltage appearing on Cin. As the voltage at the source of the MOSFET changes, capacitive coupling, via (Cgs) to the gate, causes the gate voltage to also change. The value of the gate voltage determines a magnitude of a final voltage to which the source settles. A feedback effect is thereby produced which influences the voltage transfer function of the MOSFET. A minimum voltage gain is unity. However, through a selection of capacitor values for Cin and/or Cgs, a value of gain that is greater than unity can be achieved.
摘要翻译：超低功耗增益电路（UGC）实现了源极跟随器电路的独特操作模式，并使可编程增益大于单位。 MOSFET具有耦合到输入电容（Cin）的栅极端子。 MOSFET的漏极处的电位被计时以使电荷流过通道。该电荷对连接到MOSFET源极的电容（Cout）充电。在Cout充电之后，漏极电位恢复到初始值，Cout上的电荷通过MOSFET放电，直到源极电压为栅极电位的一个阈值下降，此时MOSFET关断。 Cout然后停止放电，Cout上出现的最终电压是Cin上出现的栅极电压的大小的函数。随着MOSFET源极电压的变化，电容耦合（Cgs）到栅极，导致栅极电压也发生变化。栅极电压的值决定了源极稳定的最终电压的幅度。由此产生影响MOSFET的电压传递函数的反馈效应。最小电压增益为1。然而，通过选择Cin和/或Cgs的电容器值，可以实现大于1的增益值。

3. 发明授权

US5149954A Hold capacitor time delay and integration with equilibrating means 失效
标题翻译：保持电容器延时并与平衡装置集成
公开(公告)号：US5149954A
公开(公告)日：1992-09-22
申请号：US675231
申请日：1991-03-26
申请人： Kevin L. Pettijohn , Todd E. Sessler , John A. Stineman
发明人： Kevin L. Pettijohn , Todd E. Sessler , John A. Stineman
IPC分类号： G11C27/02 , H04N5/33 , H04N5/353 , H04N5/374 , H04N5/378
CPC分类号： H04N5/3743 , G11C27/024 , H04N3/1512 , H04N3/1525 , H04N5/33
摘要： Method and apparatus for performing a TDI function with a plurality of electrical signals. A first step of the method stores, during individual ones of a first plurality of consecutive time intervals, a sample of a first electrical signal. A second step of the method equilibrates, during individual ones of a second, subsequent plurality of time intervals, one of the stored samples with a stored sample of a second electrical signal. Subsequent to each of the steps of equilibrating, an electrical signal is outputted that has a magnitude expressive of the equilibrated stored samples. The equilibration is achieved by shorting storage capacitors (C.sub.1, C.sub.2, C.sub.3) together to effectively sum coherent signals and incoherent noise. The charge sum is stored on a capacitance that is effectively doubled from either detector channel operating individually. The output signal remains in the same range as would be an individual detector channel output voltage, without TDI, and no reduction in dynamic range is incurred.
摘要翻译：用于执行具有多个电信号的TDI功能的方法和装置。该方法的第一步骤在第一多个连续时间间隔的单独的时间段存储第一电信号的采样。该方法的第二步骤在一个秒的后续多个时间间隔的个别时间间隔期间平衡一个存储的样本，其中存储有第二电信号的样本。在平衡的每个步骤之后，输出具有表示平衡的存储样品的量值的电信号。通过将存储电容器（C1，C2，C3）短路在一起来有效地求和相干信号和非相干噪声来实现平衡。电荷总和存储在电容上，该电容从单独操作的检测器通道中有效地加倍。输出信号与单独的检测器通道输出电压保持在与TDI相同的范围内，并且不会产生动态范围的减小。

4. 发明授权

US5391868A Low power serial bias photoconductive detectors 失效
标题翻译：低功率串联偏置光电探测器
公开(公告)号：US5391868A
公开(公告)日：1995-02-21
申请号：US28505
申请日：1993-03-09
申请人： John L. Vampola , Christopher A. Hougen , Kevin L. Pettijohn
发明人： John L. Vampola , Christopher A. Hougen , Kevin L. Pettijohn
IPC分类号： H01L27/146 , H01J40/14
CPC分类号： H01L27/14643
摘要： An array (10) of photoconductive (PC) radiation detectors includes a substrate (1) and a body (12) of PC material that is disposed upon the substrate. The body of PC material has a substantially linear shape. A plurality of electrical interconnects (14, 15) are electrically coupled to the body of PC material for differentiating the body into a plurality of radiation detector sites, individual ones of the plurality of radiation detector sites being disposed in a serial arrangement with one another along a length of the body of PC material. The array further includes a bias current input terminal (16) that is electrically coupled to a first end of the body of PC material and a bias current output terminal (18) that is electrically coupled to a second end of the body of PC material. As a result, a bias current that is applied to the bias current input terminal, and that is extracted from the bias current output terminal, flows through each of the plurality of serially disposed radiation detector sites. Signal processing circuitry (32) has inputs coupled to the plurality of electrical interconnects, and includes differential amplifiers (34) for determining a difference in potential between two adjacent ones of the plurality of electrical interconnects. The difference in potential is a function of an amount radiation that is absorbed by a radiation detector site at an intervening portion of the body of PC material.
摘要翻译：光电导（PC）辐射检测器的阵列（10）包括基板（1）和布置在基板上的PC材料体（12）。 PC材料的主体具有基本线性的形状。多个电互连（14,15）电耦合到PC材料主体，用于将主体区分为多个辐射探测器位置，多个辐射探测器位置中的各个辐射探测器位置沿着串联布置沿着 PC材质的身体长度。阵列还包括电耦合到PC材料主体的第一端的偏置电流输入端子（16）和电耦合到PC材料主体的第二端的偏置电流输出端子（18）。结果，施加到偏置电流输入端并且从偏置电流输出端提取的偏置电流流过多个串联设置的辐射探测器位置中的每一个。信号处理电路（32）具有耦合到多个电互连的输入，并且包括用于确定多个电互连中的两个相邻电互连之间的电位差的差分放大器（34）。电位差是由PC材料的主体的中间部分被辐射检测器部位吸收的量的辐射的函数。

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