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1. 发明授权

US5784604A Method and system for reduced run-time delay during conditional branch execution in pipelined processor systems utilizing selectively delayed sequential instruction purging 失效
标题翻译：用于利用选择性延迟顺序指令清除在流水线处理器系统中的条件分支执行期间减少运行时间延迟的方法和系统
公开(公告)号：US5784604A
公开(公告)日：1998-07-21
申请号：US959183
申请日：1992-10-09
申请人： John Stephen Muhich , Terrence Matthew Potter , Steven Wayne White
发明人： John Stephen Muhich , Terrence Matthew Potter , Steven Wayne White
IPC分类号： G06F9/38 , G06F9/00
CPC分类号： G06F9/3804
摘要： A method and system are disclosed for reducing run-time delay during conditional branch instruction execution in a pipelined processor system. A series of queued sequential instructions and conditional branch instructions are processed wherein each conditional branch instruction specifies an associated conditional branch to be taken in response to a selected outcome of processing one or more sequential instructions. Upon detection of a conditional branch instruction within the queue, a group of target instructions are fetched based upon a prediction that an associated conditional branch will be taken. Sequential instructions within the queue following the conditional branch instruction are then purged and the target instructions loaded into the queue only in response to a successful a retrieval of the target instructions, such that the sequential instructions may be processed without delay if the prediction that the conditional branch is taken proves invalid prior to retrieval of the target instructions. Alternately, the purged sequential instructions may be refetched after loading the target instructions such that the sequential instructions may be executed with minimal delay if the prediction that the conditional branch is taken proves invalid after loading the target instructions. In yet another embodiment, the sequential instructions within the queue following the conditional branch instruction are purged only in response to a successful retrieval of the target instructions and an imminent execution of the conditional branch instruction.
摘要翻译：公开了一种用于在流水线处理器系统中的条件分支指令执行期间减少运行时间延迟的方法和系统。处理一系列排队的顺序指令和条件分支指令，其中每个条件分支指令响应于处理一个或多个顺序指令的所选结果来指定要采取的相关联的条件分支。在检测到队列内的条件分支指令之后，基于将采用相关联的条件分支的预测来取得一组目标指令。随后条件分支指令之后的队列中的顺序指令被清除，并且目标指令仅仅响应于目标指令的成功检索而被加载到队列中，使得如果预测条件在检索目标指令之前，分支被认为是无效的。或者，可以在加载目标指令之后重新抽取清除的顺序指令，使得如果在加载目标指令之后条件分支的预测被证明是无效的，则可以以最小延迟执行顺序指令。在另一个实施例中，仅在响应于目标指令的成功检索和条件分支指令的即将执行之后才清除在条件分支指令之后的队列内的顺序指令。

2. 发明授权

US5860014A Method and apparatus for improved recovery of processor state using history buffer 失效
标题翻译：使用历史缓冲区来改善处理器状态恢复的方法和装置
公开(公告)号：US5860014A
公开(公告)日：1999-01-12
申请号：US729307
申请日：1996-10-15
申请人： Hoichi Cheong , Hung Qui Le , John Stephen Muhich , Steven Wayne White
发明人： Hoichi Cheong , Hung Qui Le , John Stephen Muhich , Steven Wayne White
IPC分类号： G06F9/38 , G06F9/46
CPC分类号： G06F9/3861
摘要： A method and apparatus for maintaining content of registers of a processor which uses the registers for processing instructions. Entries are stored in a buffer for restoring register content in response to an interruption by an interruptible instruction. Entries include information for reducing the number of entries selected for the restoring. A set of the buffer entries is selected, in response to the interruption and the information, for restoring register content. The set includes only entries which are necessary for restoring the content in response to the interruption so that the content of the processor registers may be restored in a single processor cycle, even if multiple entries are stored for a first one of the registers and multiple entries are stored for a second one of the registers.
摘要翻译：一种用于维护使用寄存器处理指令的处理器的寄存器的内容的方法和装置。条目存储在缓冲器中，用于通过可中断指令中断来恢复寄存器内容。条目包括用于减少为恢复选择的条目数量的信息。响应于中断和信息来选择一组缓冲器条目用于恢复寄存器内容。该集合仅包括为了响应于中断而恢复内容所必需的条目，使得处理器寄存器的内容可以在单个处理器周期中被恢复，即使对于第一个寄存器和多个条目存储了多个条目存储在第二个寄存器中。

3. 发明授权

US6079002A Dynamic expansion of execution pipeline stages 失效
标题翻译：执行流水线阶段的动态扩展
公开(公告)号：US6079002A
公开(公告)日：2000-06-20
申请号：US935573
申请日：1997-09-23
申请人： Larry Edward Thatcher , John Stephen Muhich , Steven Wayne White , Troy Neal Hicks
发明人： Larry Edward Thatcher , John Stephen Muhich , Steven Wayne White , Troy Neal Hicks
IPC分类号： G06F9/38 , G06F12/00
CPC分类号： G06F9/3867 , G06F9/3824
摘要： A method and system in a data processing system for accessing information using an instruction specifying a memory address is disclosed. The method and system comprises issuing the instruction to an execution unit and storing an address derived from the specified address. The method and system also includes accessing a cache to obtain the information, using the derived address and determining, in response to a signal indicating that there has been a cache miss, if there is a location available to store the specified address in a queue. According to the system and method disclosed herein, the present invention allows for dynamic pipeline expansion of a processor without splitting this function between components depending upon the reason expansion was required, thereby increasing overall system performance.
摘要翻译：公开了一种使用指定存储器地址的指令访问信息的数据处理系统中的方法和系统。该方法和系统包括向执行单元发出指令并存储从指定地址导出的地址。该方法和系统还包括访问高速缓存以获得信息，使用导出的地址并且响应于指示已经存在高速缓存未命中的信号确定是否存在可用于将指定的地址存储在队列中的位置。根据本文公开的系统和方法，根据需要扩展的原因，本发明允许处理器的动态管道扩展，而不会在组件之间分离该功能，从而提高整体系统性能。

4. 发明授权

US6167500A Mechanism for queuing store data and method therefor 失效
标题翻译：排队存储数据的机制及其方法
公开(公告)号：US6167500A
公开(公告)日：2000-12-26
申请号：US131789
申请日：1998-08-10
申请人： Kurt Alan Feiste , John Stephen Muhich , Steven Wayne White
发明人： Kurt Alan Feiste , John Stephen Muhich , Steven Wayne White
IPC分类号： G06F9/38 , G06F12/00
CPC分类号： G06F9/3867 , G06F9/3824
摘要： A mechanism and method for a store data queue are implemented. Address translation operations for store instructions in a data processor are decoupled from data operations by initiating address translation before source data operands are available. A store data queue snoops the finish buses of execution units for the source operand. A data entry in the data queue that is allocated at dispatch of the store instruction snoops for the source operand required by its corresponding instruction. The data operand is then communicated to a memory device in instruction order thereby simplifying the detection of conflicting stores.
摘要翻译：实现了存储数据队列的机制和方法。数据处理器内存储指令的地址转换操作通过在源数据操作数可用之前发起地址转换与数据操作分离。存储数据队列窥探源操作数的执行单元的完成总线。数据队列中的数据条目，在其对应指令所要求的源操作数的分派中分配存储指令侦听。然后以指令顺序将数据操作数传送到存储器件，从而简化了冲突存储的检测。

5. 发明授权

US6021485A Forwarding store instruction result to load instruction with reduced stall or flushing by effective/real data address bytes matching 失效
标题翻译：通过有效/实际数据地址字节匹配，将存储指令结果转发到加载指令，减少停止或刷新
公开(公告)号：US6021485A
公开(公告)日：2000-02-01
申请号：US826854
申请日：1997-04-10
申请人： Kurt Alan Feiste , John Stephen Muhich , Larry Edward Thatcher , Steven Wayne White
发明人： Kurt Alan Feiste , John Stephen Muhich , Larry Edward Thatcher , Steven Wayne White
IPC分类号： G06F9/38 , G06F12/00 , G06F9/34
CPC分类号： G06F9/3816 , G06F9/30079 , G06F9/3824 , G06F9/3826 , G06F9/3834 , G06F9/384 , G06F9/3842 , G06F9/3855 , G06F9/3863
摘要： In a superscalar processor implementing out-of-order dispatching and execution of load and store instructions, when a store instruction has already been translated, the load address range of a load instruction is contained within the address range of the store instruction, and the data associated with the store instruction is available, then the data associated with the store instruction is forwarded to the load instruction so that the load instruction may continue execution without having to be stalled or flushed.
摘要翻译：在执行无序调度和执行加载和存储指令的超标量处理器中，当存储指令已经被翻译时，加载指令的加载地址范围包含在存储指令的地址范围内，并且数据与存储指令相关联的可用，则与存储指令相关联的数据被转发到加载指令，使得加载指令可以继续执行而不必被停止或刷新。

6. 发明授权

US5931957A Support for out-of-order execution of loads and stores in a processor 失效
标题翻译：支持处理器中负载和存储的无序执行
公开(公告)号：US5931957A
公开(公告)日：1999-08-03
申请号：US829669
申请日：1997-03-31
申请人： Brian R Konigsburg , John Stephen Muhich , Larry Edward Thatcher , Steven Wayne White
发明人： Brian R Konigsburg , John Stephen Muhich , Larry Edward Thatcher , Steven Wayne White
IPC分类号： G06F9/312 , G06F9/38 , G06F11/00 , G06F9/30
CPC分类号： G06F9/30043 , G06F9/3834 , G06F9/3861
摘要： To support load instructions which execute out-of-order with respect to store instructions, a mechanism is implemented to detect (and correct) the occurrences where a load instruction executed prior to a logically prior store instruction, and where the load instruction received data for the location prior to being modified by the store instruction, and the correct data for the load instruction included bytes from the store instruction. Additionally, to execute store instructions out-of-order with respect to load instructions, a mechanism is implemented to keep a store instruction from destroying data that will be used by a logically earlier load instruction. Further, to support load instructions that are executed out-of-order with respect to each other, a mechanism is implemented to insure that any pair of load instructions (which access at least one byte in common) return data consistent with executing the load instructions in order.
摘要翻译：为了支持关于存储指令执行无序的加载指令，实现了一种机制来检测（和校正）在逻辑上先前的存储指令之前执行的加载指令的发生，并且其中加载指令接收数据为由存储指令修改之前的位置，以及加载指令的正确数据，包括来自存储指令的字节。另外，为了执行与加载指令无序的存储指令，实现了一种机制来保持存储指令不会破坏由逻辑上较早的加载指令使用的数据。此外，为了支持相对于彼此执行的无序执行的加载指令，实现一种机制以确保任何一对加载指令（其访问至少一个共同的字节）返回数据与执行加载指令一致为了。

7. 发明授权

US5870582A Method and apparatus for completion of non-interruptible instructions before the instruction is dispatched 失效
标题翻译：在发出指令前完成不可中断指令的方法和装置
公开(公告)号：US5870582A
公开(公告)日：1999-02-09
申请号：US829671
申请日：1997-03-31
申请人： Hoichi Cheong , Hung Qui Le , John Stephen Muhich , Steven Wayne White
发明人： Hoichi Cheong , Hung Qui Le , John Stephen Muhich , Steven Wayne White
IPC分类号： G06F9/38
CPC分类号： G06F9/3855 , G06F9/3836 , G06F9/384 , G06F9/3853 , G06F9/3857 , G06F9/3863
摘要： In a method and apparatus for allocating processor resources in a data processing system, instructions are dispatched and tagged for processing. A processor resource snoops to obtain execution results for the tagged instructions. Such an instruction is logically "finished" in response to determining that it will not cause an interrupt (which includes not changing the sequence of completing instructions), and "completed" in response to finishing all earlier dispatched instructions. Information is entered for such an instructions in rename buffer in response to the instruction targeting an architected register, and such a rename buffer entry is released in response to completing the entry's instruction. The rename buffer may comprise a history buffer. Also, information for the instructions is entered in a completion queue in response to dispatching the instructions, and the queue entry for such an instruction is released in response to completion of the instruction. Also, the instructions are grouped, a group having solely a single interruptible instruction, and further including non-interruptible instructions dispatched following the interruptible instruction. Thus, there may be numerous non-interruptible instructions in such a group. Such an interruptible instruction is logically "finished" in response to determining that it will not cause an interrupt, and "completed" in response to finishing all earlier dispatched instructions. Such a non-interruptible instruction is logically "finished" and "completed" in response to completion of its associated interruptible instruction, so that such a non-interruptible instruction may complete before it is dispatched.
摘要翻译：在用于在数据处理系统中分配处理器资源的方法和装置中，调度和标记用于处理的指令。处理器资源被窥探以获得标记指令的执行结果。响应于确定不会导致中断（其不包括改变完成指令的顺序），并且响应于完成所有先前分派的指令而“完成”，这样的指令在逻辑上“完成”。响应于针对架构化寄存器的指令，在重命名缓冲器中输入这样的指令的信息，并且响应于完成条目的指令而释放这样的重命名缓冲器条目。重命名缓冲器可以包括历史缓冲器。此外，响应于分派指令，将指令的信息输入到完成队列中，并且响应于指令的完成而释放这样的指令的队列条目。此外，指令被分组，仅具有单个可中断指令的组，并且还包括在可中断指令之后分派的不可中断指令。因此，在这样的组中可能存在许多不可中断的指令。这种可中断指令在逻辑上“完成”以响应于确定它不会引起中断，并且响应于完成所有先前分派的指令而“完成”。响应于其相关联的可中断指令的完成，这种不可中断指令被逻辑地“完成”和“完成”，使得这种不可中断指令可以在其被分派之前完成。

8. 发明授权

US5864341A Instruction dispatch unit and method for dynamically classifying and issuing instructions to execution units with non-uniform forwarding 失效
标题翻译：指令调度单元和方法，用于向不均匀转发的执行单元动态分类和发布指令
公开(公告)号：US5864341A
公开(公告)日：1999-01-26
申请号：US761875
申请日：1996-12-06
申请人： Troy Neal Hicks , Hung Qui Le , John Stephen Muhich , Steven Wayne White
发明人： Troy Neal Hicks , Hung Qui Le , John Stephen Muhich , Steven Wayne White
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3891 , G06F9/3824 , G06F9/3853 , G06F9/3885
摘要： The present invention is directed to a method and apparatus for dispatching instructions in an information handling system. A pre-execution queue stores instructions, and at least one execution cluster is operably coupled to the pre-execution queue. An execution cluster comprises an early execution unit for executing a first instruction dispatched from the pre-execution queue to generate and forward a first result and a late execution unit for executing a second instruction dispatched from the pre-execution queue to generate and forward a second result after the first execution unit forwards the first result. The invention further includes circuitry operably associated with the pre-execution queue, and a method for prioritizing the order in which the instructions in the pre-execution queue are dispatched to the execution cluster.
摘要翻译：本发明涉及一种用于在信息处理系统中调度指令的方法和装置。预执行队列存储指令，并且至少一个执行群集可操作地耦合到预执行队列。执行群包括一个早期执行单元，用于执行从预执行队列发出的第一指令，以产生和转发第一结果;以及后期执行单元，用于执行从预执行队列发出的第二指令，以产生和转发第二个第一执行单元转发第一个结果后的结果。本发明还包括可操作地与预执行队列相关联的电路，以及用于将预执行队列中的指令分派到执行群集的顺序的优先级的方法。

9. 发明授权

US06266767B1 Apparatus and method for facilitating out-of-order execution of load instructions 有权
标题翻译：用于促进装载指令的无序执行的装置和方法
公开(公告)号：US06266767B1
公开(公告)日：2001-07-24
申请号：US09296871
申请日：1999-04-22
申请人： Kurt Alan Feiste , John Stephen Muhich , Steven Wayne White
发明人： Kurt Alan Feiste , John Stephen Muhich , Steven Wayne White
IPC分类号： G06F9312
CPC分类号： G06F9/3855 , G06F9/383 , G06F9/3834 , G06F9/3842
摘要： A processor (100) includes a preload queue (160) for storing a plurality of preload entries. Each preload entry is associated with a preload instruction and includes the address and byte count defined by the respective preload and an identifier associated with the respective preload. A comparison unit (170) associated with the preload queue (160) identifies each conflicting preload entry, that is, each preload entry associated with a preload instruction that conflicts with an older store instruction. The oldest preload instruction associated with one of the conflicting preload entries represents a target preload. The processor (100) may flush this target preload along with all instructions executed after the target preload in order to correct for the conflict between the target preload and store instruction.
摘要翻译：处理器（100）包括用于存储多个预加载条目的预加载队列（160）。每个预加载条目与预加载指令相关联，并且包括由相应的预载荷定义的地址和字节计数以及与相应的预载荷相关联的标识符。与预加载队列（160）相关联的比较单元（170）识别每个冲突的预加载条目，即与与旧存储指令冲突的预加载指令相关联的每个预加载条目。与其中一个冲突的预加载条目相关联的最早的预加载指令表示目标预加载。处理器（100）可以与目标预加载之后执行的所有指令一起刷新该目标预载荷，以便校正目标预加载和存储指令之间的冲突。

10. 发明授权

US6098167A Apparatus and method for fast unified interrupt recovery and branch recovery in processors supporting out-of-order execution 失效
标题翻译：支持无序执行的处理器的快速统一中断恢复和分支恢复的装置和方法
公开(公告)号：US6098167A
公开(公告)日：2000-08-01
申请号：US829667
申请日：1997-03-31
申请人： Hoichi Cheong , Hung Qui Le , John Stephen Muhich , Steven Wayne White
发明人： Hoichi Cheong , Hung Qui Le , John Stephen Muhich , Steven Wayne White
IPC分类号： G06F9/38 , G06F9/46
CPC分类号： G06F9/3863
摘要： In maintaining the state of a processor, a dispatched instruction is given an identification tag and an associated entry in an architectural register table. The identification tag of the dispatched instruction is written to the entry in the architectural register table, if the identification tag of the dispatched instruction is more recent than a prior instruction identification tag stored in the entry.
摘要翻译：在维护处理器的状态时，在架构寄存器表中给出分派指令的识别标签和相关联的条目。如果调度指令的识别标签比存储在条目中的先前指令标识标签更新，则将调度指令的识别标签写入架构寄存器表中的条目。

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