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1. 发明授权

US5051885A Data processing system for concurrent dispatch of instructions to multiple functional units 失效
标题翻译：数据处理系统，用于将指令并发发送到多个功能单元
公开(公告)号：US5051885A
公开(公告)日：1991-09-24
申请号：US255105
申请日：1988-10-07
申请人： John S. Yates, Jr. , Stephen J. Ciavaglia , John Manton , Michael Kahaiyan , Richard G. Bahr , Barry J. Flahive
发明人： John S. Yates, Jr. , Stephen J. Ciavaglia , John Manton , Michael Kahaiyan , Richard G. Bahr , Barry J. Flahive
IPC分类号： G06F9/30 , G06F9/32 , G06F9/38 , G06F15/16
CPC分类号： G06F9/3889 , G06F9/30149 , G06F9/321 , G06F9/3814 , G06F9/3816 , G06F9/3853 , G06F9/3885
摘要： Apparatus and method for concurrent dispatch of instruction words which selectively comprise instruction components which are separately and substantially simultaneously received by distinct floating point and integer functional units. The instruction words are powers of 2 in length, (measured in terms of the smallest machine addressable unit) typically a 4 byte longword and an 8 byte quadword aligned to the natural boundaries also corresponding to powers of 2. To provide maximum operating efficiency, each functional (or processing) unit executes a component of an instruction word during an execution cycle. The type and length of the instruction word are indicated by one of the bit fields of the instruction word, which permits the apparatus to properly detect, store and transfer the instruction word to the appropriate functional unit. The invention combines the encoding efficiency of variable length instruction combined combined with the enhanced processing speed of simultaneous operation of all available functional units, to provide the execution efficiency of systems with a single instruction length.

2. 发明授权

US5045992A Apparatus for executing instruction regardless of data types and thereafter selectively branching to other instruction upon determining of incompatible data type 失效
标题翻译：用于执行指令而不管数据类型，然后在确定不兼容的数据类型时选择性地分支到其他指令的装置
公开(公告)号：US5045992A
公开(公告)日：1991-09-03
申请号：US259792
申请日：1988-10-19
申请人： John S. Yates, Jr. , Stephen J. Ciavaglia
发明人： John S. Yates, Jr. , Stephen J. Ciavaglia
IPC分类号： G06F9/38 , G06F9/318 , G06F9/44
CPC分类号： G06F9/30192 , G06F8/312 , G06F9/3889
摘要： A method and apparatus for improving the efficiency of executing arithmetic and logical operations performed on arguments provided during the execution of computer instructions in which operands include a variable type argument or data portion accompanied by a tag identifier which defines the data type. The processing of the data is enhanced by the addition of two condition codes derived from the values of the pre-ALU tag identifiers and the post-ALU results. The condition codes allow rapid determination of data types without additional execution cycles or hardware overhead, resulting in enhanced execution of the instructions.

3. 发明授权

US08788792B2 Apparatus for executing programs for a first computer architecture on a computer of a second architecture 有权
标题翻译：一种用于在第二架构的计算机上执行用于第一计算机体系结构的程序的装置
公开(公告)号：US08788792B2
公开(公告)日：2014-07-22
申请号：US13371766
申请日：2012-02-13
申请人： John S. Yates, Jr. , Matthew F. Storch , Sandeep Nijhawan , Dale R. Jurich , Korbin S. Van Dyke
发明人： John S. Yates, Jr. , Matthew F. Storch , Sandeep Nijhawan , Dale R. Jurich , Korbin S. Van Dyke
IPC分类号： G06F9/30 , G06F9/40 , G06F15/00
CPC分类号： G06F9/45554 , G06F9/30174 , G06F9/30189 , G06F9/3861
摘要： A multi-instruction set architecture (ISA) computer system includes a computer program, a first processor, a second processor, a profiler, and a translator. The computer program includes instructions of a first ISA, the first ISA having a first complexity. The first processor is configured to execute instructions of the first ISA. The second processor is configured to execute instructions of a second ISA, the second ISA being different than the first ISA and having a second complexity, wherein the second complexity is less than the first complexity. The profiler is configured to select a block of the computer program for translation to instructions of the second ISA, wherein the block includes one or more instructions of the first ISA. The translator is configured to translate the block of the first ISA into instructions of the second ISA for execution by the second processor.
摘要翻译：多指令集架构（ISA）计算机系统包括计算机程序，第一处理器，第二处理器，轮廓仪和翻译器。计算机程序包括第一ISA的指令，第一ISA具有第一复杂度。第一处理器被配置为执行第一ISA的指令。第二处理器被配置为执行第二ISA的指令，第二ISA不同于第一ISA并且具有第二复杂度，其中第二复杂度小于第一复杂度。分析器被配置为选择用于转换为第二ISA的指令的计算机程序的块，其中该块包括第一ISA的一个或多个指令。翻译器被配置为将第一ISA的块转换为第二ISA的指令以供第二处理器执行。

4. 发明授权

US06954923B1 Recording classification of instructions executed by a computer 有权
标题翻译：记录计算机执行指令的分类
公开(公告)号：US06954923B1
公开(公告)日：2005-10-11
申请号：US09348317
申请日：1999-07-07
申请人： John S. Yates, Jr. , David L. Reese , Korbin S. Van Dyke
发明人： John S. Yates, Jr. , David L. Reese , Korbin S. Van Dyke
IPC分类号： G06F9/318 , G06F9/38 , G06F9/42 , G06F9/44
CPC分类号： G06F9/3851 , G06F9/30174 , G06F9/30189 , G06F9/3802 , G06F9/3861 , G06F9/4486
摘要： An instruction processor to execute two instruction sets. Instructions are stored in different virtual memory pages of a single address space, and are coded for computers of two different instruction sets, and use of two different calling conventions. The instruction processor interprets instructions under, alternately, the first or second instruction set as directed by a first flag stored in table entries corresponding to memory pages for the instructions. The processor recognizes when program execution has transferred from a page of instructions using the first data storage convention to a page of instructions using the second data storage convention, as indicated by a second flag stored in the table entries, and then adjusts a data storage content of the computer from the first storage convention to the second data storage convention. A history record provides a record of a classification of a recently-executed instruction.
摘要翻译：一个执行两个指令集的指令处理器。指令存储在单个地址空间的不同虚拟存储器页面中，并且被编码用于两个不同指令集的计算机，并且使用两种不同的调用约定。指令处理器根据存储在对应于指令的存储器页的表条目中的第一标志的指示，来解释第一或第二指令集下的指令。处理器识别何时使用第二数据存储约定将使用第一数据存储约定的指令页面的程序执行转移到指令页，如由表条目中存储的第二标志所指示的，然后调整数据存储内容的计算机从第一存储惯例到第二数据存储惯例。历史记录提供了最近执行的指令的分类记录。

5. 发明授权

US06374341B1 Apparatus and a method for variable size pages using fixed size translation lookaside buffer entries 有权
标题翻译：使用固定大小翻译后备缓冲区条目的可变大小页面的装置和方法
公开(公告)号：US06374341B1
公开(公告)日：2002-04-16
申请号：US09146484
申请日：1998-09-02
申请人： Sandeep Nijhawan , Denis Gulsen , John S. Yates, Jr.
发明人： Sandeep Nijhawan , Denis Gulsen , John S. Yates, Jr.
IPC分类号： G06F1210
CPC分类号： G06F12/1027 , G06F2212/652
摘要： The present invention provides an apparatus and a method for variable size pages using fixed size TLB (Translation Lookaside Buffer) entries. In one embodiment, an apparatus for variable size pages using fixed size TLB entries includes a first TLB for fixed size pages and a second TLB for variable size pages. In particular, the second TLB stores fixed size TLB entries for variable size pages. Further, in one embodiment, an input of an OR device is connected to the second TLB to provide a cost-effective and efficient implementation for translating linear addresses to physical addresses using fixed size TLB entries stored in the second TLB.
摘要翻译：本发明提供一种使用固定大小的TLB（翻译后备缓冲器）条目的可变尺寸页面的装置和方法。在一个实施例中，使用固定大小的TLB条目的可变大小页面的装置包括用于固定大小页面的第一TLB和用于可变大小页面的第二TLB。特别地，第二TLB存储可变大小页面的固定大小的TLB条目。此外，在一个实施例中，OR设备的输入连接到第二TLB，以提供使用存储在第二TLB中的固定大小的TLB条目将线性地址转换为物理地址的成本有效且有效的实现。

6. 发明授权

US07069421B1 Side tables annotating an instruction stream 有权
标题翻译：侧表注释指令流
公开(公告)号：US07069421B1
公开(公告)日：2006-06-27
申请号：US09429094
申请日：1999-10-28
申请人： John S. Yates, Jr. , David L. Reese , Paul H. Hohensee , Korbin S. Van Dyke , T. R. Ramesh
发明人： John S. Yates, Jr. , David L. Reese , Paul H. Hohensee , Korbin S. Van Dyke , T. R. Ramesh
IPC分类号： G06F9/30
CPC分类号： G06F9/45533
摘要： A microprocessor chip, and methods for use in that microprocessor chip. The chip has instruction pipeline circuitry and address translation circuitry. Table lookup circuitry indexes into a table, the table having an entry associated with each corresponding address range translated by the address translation circuitry. Each entry of the table describes a likelihood of the existence of an alternate coding of instructions located in the respective corresponding address range. The table lookup circuitry retrieves a table entry corresponding to the address, and is operable as part of the basic instruction cycle of executing an instruction of a non-supervisor mode program executing on a computer. Interrupt circuitry is cooperatively designed with the instruction pipeline circuitry to trigger an interrupt on execution of an instruction of a process, synchronously based at least in part on a memory state of the computer and the address of the instruction, the architectural definition of the instruction not calling for an interrupt. A handler for the interrupt is responsive to the contents of the table to affect the instruction pipeline circuitry to effect control of an architecturally-visible data manipulation behavior or control transfer behavior of the instruction based on the contents of a table entry associated with the instruction.
摘要翻译：微处理器芯片，以及用于该微处理器芯片的方法。该芯片具有指令流水线电路和地址转换电路。表查找电路索引到表中，该表具有与由地址转换电路翻译的每个相应地址范围相关联的条目。该表的每个条目描述存在位于相应的相应地址范围内的指令的替代编码的可能性。表查找电路检索对应于该地址的表条目，并可作为执行在计算机上执行的非主管模式程序的指令的基本指令周期的一部分。中断电路与指令流水线电路协同设计，以至少部分地基于计算机的存储状态和指令的地址同步地触发执行过程指令的中断，指令的架构定义不是要求中断。用于中断的处理程序响应于表的内容，以影响指令流水线电路，以基于与该指令相关联的表条目的内容来实现对结构上可视数据操纵行为的控制或指令的控制传递行为。

7. 发明授权

US06826748B1 Profiling program execution into registers of a computer 有权
标题翻译：将程序执行分析到计算机的寄存器中
公开(公告)号：US06826748B1
公开(公告)日：2004-11-30
申请号：US09339749
申请日：1999-06-24
申请人： Paul H. Hohensee , David L. Reese , John S. Yates, Jr. , Korbin S. Van Dyke , T. R. Ramesh , Shalesh Thusoo , Gurjeet Singh Saund , Niteen Aravind Patkar
发明人： Paul H. Hohensee , David L. Reese , John S. Yates, Jr. , Korbin S. Van Dyke , T. R. Ramesh , Shalesh Thusoo , Gurjeet Singh Saund , Niteen Aravind Patkar
IPC分类号： G06F944
CPC分类号： G06F9/45558 , G06F9/45541 , G06F9/45554 , G06F2009/45583
摘要： A method and computer for performance of the method. While executing a program on a computer, the computer uses registers of a general register file for storage of instruction results. Profile information describing the profileable events is recorded into the general register file as the profileable events occur, without first capturing the information into a main memory of the computer.
摘要翻译：用于执行该方法的方法和计算机。在计算机上执行程序时，计算机使用通用寄存器文件的寄存器来存储指令结果。描述可概要事件的简档信息可记录在通用寄存器文件中，因为可以描述事件的发生，而无需先将信息捕获到计算机的主存储器中。

8. 发明授权

US06763452B1 Modifying program execution based on profiling 有权
标题翻译：基于分析修改程序执行
公开(公告)号：US06763452B1
公开(公告)日：2004-07-13
申请号：US09339797
申请日：1999-06-24
申请人： Paul H. Hohensee , John S. Yates, Jr. , Korbin S. Van Dyke , David L. Reese , Stephen C. Purcell
发明人： Paul H. Hohensee , John S. Yates, Jr. , Korbin S. Van Dyke , David L. Reese , Stephen C. Purcell
IPC分类号： G06F900
CPC分类号： G06F9/45558 , G06F9/45541 , G06F9/45554 , G06F2009/45583
摘要： A method and a multiprocessor computer for execution of the method. A first CPU has a general register file, an instruciton pipeline, and profile circuitry. The profile circuitry is operatively interconnected and under common hardware control with the instruction pipeline. The profile circuitry and instruction pipeline are cooperatively interconnected to detect the occurrence of profileable events occurring in the instruction pipeline. The profile circuitry is operable without software intervention to effect recording of profile information describing the profileable events into the general register file, without first capturing the information into a main memory of the computer. The recording is essentially concurrent with the occurrence of the profileable events. A second CPU is configured to analyze the generated profile data, while the execution and profile data generation continue on the first CPU, and to control the execution of the program on the first CPU based at least in part on the analysis of the collected profile data.
摘要翻译：一种用于执行该方法的方法和多处理器计算机。第一个CPU有一个通用寄存器文件，一个通道管道和一个轮廓电路。配置文件电路与指令管道可操作地互连，并在通用的硬件控制下。配置文件电路和指令流水线协同互连，以检测在指令流水线中发生的可轮廓事件的发生。配置文件电路可操作而无需软件干预，以便将描述可描述事件的简档信息记录到通用寄存器文件中，而无需首先将信息捕获到计算机的主存储器中。录音本质上与可配置事件的发生同时发生。第二CPU被配置为分析生成的简档数据，同时在第一CPU上继续执行和简档数据生成，并且至少部分地基于所收集的简档数据的分析来控制第一CPU上的程序的执行。

9. 发明授权

US07065633B1 System for delivering exception raised in first architecture to operating system coded in second architecture in dual architecture CPU 有权
标题翻译：用于将第一架构中提出的异常提交给在双架构CPU中的第二架构中编码的操作系统的系统
公开(公告)号：US07065633B1
公开(公告)日：2006-06-20
申请号：US09626325
申请日：2000-07-26
申请人： John S. Yates, Jr. , Matthew F. Storch , Sandeep Nijhawan , Dale R. Jurich , Korbin S. Van Dyke
发明人： John S. Yates, Jr. , Matthew F. Storch , Sandeep Nijhawan , Dale R. Jurich , Korbin S. Van Dyke
IPC分类号： G06F9/00
CPC分类号： G06F9/3822 , G06F9/30123 , G06F9/30167 , G06F9/30174 , G06F9/30189 , G06F9/30196
摘要： A computer concurrently executes a first operating system coded in a RISC instruction set and a second operating system coded in a CISC instruction set. When an exception is raised while executing a program coded in the RISC instruction set, an execution thread may be initiated under the CISC operating system. The exception may be delivered to the initiated thread for handling by the CISC operating system.
摘要翻译：计算机同时执行以RISC指令集编码的第一操作系统和以CISC指令集编码的第二操作系统。当执行在RISC指令集中编码的程序发生异常时，可以在CISC操作系统下启动执行线程。该异常可能被传送到由CISC操作系统处理的发起的线程。

10. 发明授权

US07013456B1 Profiling execution of computer programs 有权
标题翻译：分析计算机程序的执行情况
公开(公告)号：US07013456B1
公开(公告)日：2006-03-14
申请号：US09334530
申请日：1999-06-16
申请人： Korbin S. Van Dyke , Paul H. Hohensee , David L. Reese , John S. Yates, Jr. , T. R. Ramesh , Shalesh Thusoo , Gurjeet Singh Saund , Stephen C. Purcell , Niteen Aravind Patkar
发明人： Korbin S. Van Dyke , Paul H. Hohensee , David L. Reese , John S. Yates, Jr. , T. R. Ramesh , Shalesh Thusoo , Gurjeet Singh Saund , Stephen C. Purcell , Niteen Aravind Patkar
IPC分类号： G06F9/44
CPC分类号： G06F9/45533 , G06F9/45541 , G06F9/45554
摘要： A method and a computer for performance of the method. While executing a program on a computer, profileable events occurring in the instruction pipeline are detected. The instruction pipeline is directed to record profile information describing the profileable events essentially concurrently with the occurrence of the profileable events. The detecting and recording occur under control of hardware of the computer without software intervention.
摘要翻译：一种用于执行该方法的方法和计算机。在计算机上执行程序时，检测到在指令流水线中发生的可轮廓事件。该指令流水线用于记录描述可概要事件的简档信息，基本上与可概要事件的发生同时发生。检测和记录在没有软件干预的情况下在计算机硬件的控制下进行。

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