专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07064528B2 Droop amplifier circuit 有权
标题翻译： Droop放大器电路
公开(公告)号：US07064528B2
公开(公告)日：2006-06-20
申请号：US10854357
申请日：2004-05-26
申请人： Thomas A. Jochum , John S. Kleine
发明人： Thomas A. Jochum , John S. Kleine
IPC分类号： G05F1/44
CPC分类号： H02M3/1584
摘要： A droop amplifier circuit for a DC-DC regulator including an amplifier, at least one first resistive device, a second resistive device, a third resistive device, and a first capacitive device. Each first resistive device is coupled between an output inductor (phase node or current sense node) and the amplifier's non-inverting input. The first capacitive device is coupled between the regulator output and the amplifier's output. The second resistive device is coupled between the regulator output and the amplifier's inverting input. The third resistive device is coupled between the amplifier's inverting input and output. A second capacitive device may be coupled between the regulator output and the amplifier's non-inverting input. A fourth resistive device may be coupled in parallel with the second capacitive device. A relatively small, simple and low performing amplifier is sufficient. Circuit area and power are reduced, and low input offset voltage is more easily achieved.
摘要翻译：一种用于DC-DC调节器的下降放大器电路，包括放大器，至少一个第一电阻器件，第二电阻器件，第三电阻器件和第一电容器件。每个第一电阻器件耦合在输出电感器（相位节点或电流检测节点）和放大器的同相输入之间。第一电容器件耦合在调节器输出和放大器的输出之间。第二电阻器件耦合在调节器输出端和放大器的反相输入端之间。第三电阻器件耦合在放大器的反相输入和输出之间。第二电容器件可以耦合在调节器输出和放大器的非反相输入之间。第四电阻器件可以与第二电容器件并联耦合。相对较小，简单且性能低的放大器就足够了。电路面积和功率降低，输入失调电压较低。

2. 发明授权

US08269474B2 System and method for reducing voltage overshoot during load release within a buck regulator 有权
标题翻译：降压调节器中负载释放期间减小电压过冲的系统和方法
公开(公告)号：US08269474B2
公开(公告)日：2012-09-18
申请号：US12506722
申请日：2009-07-21
申请人： John S. Kleine
发明人： John S. Kleine
IPC分类号： G05F1/00
CPC分类号： H02M3/158
摘要： A buck regulator comprises an upper switching transistor connected between a voltage input node and a phase node. A lower switching transistor is connected between the phase node and a ground node. An inductor is connected between the phase node and an output voltage node. Circuitry generates control signals to the upper switching transistor and the lower switching transistor responsive to the output voltage and a reference voltage. The control signals to the lower switching transistor selectively turn off the lower switching transistor responsive to a current direction through the lower switching transistor and an indication of whether a voltage error signal has been clamped at a selected level.
摘要翻译：降压调节器包括连接在电压输入节点和相位节点之间的上开关晶体管。下切换晶体管连接在相位节点和接地节点之间。电感器连接在相位节点和输出电压节点之间。电路根据输出电压和参考电压产生控制信号到上开关晶体管和下开关晶体管。响应于通过下开关晶体管的电流方向，向下开关晶体管的控制信号选择性地关断下开关晶体管，并且指示电压误差信号是否被钳位在选定电平。

3. 发明授权

US07161332B1 Removing a phase in multiphase DC/DC converter without disturbing the output voltage 有权
标题翻译：去除多相DC / DC转换器中的相，而不会干扰输出电压
公开(公告)号：US07161332B1
公开(公告)日：2007-01-09
申请号：US11225532
申请日：2005-09-13
申请人： John S. Kleine , Thomas A. Jochum
发明人： John S. Kleine , Thomas A. Jochum
IPC分类号： G05F1/652 , G05F1/656
CPC分类号： H02M3/1584 , H02M2001/0032 , H02M2001/008 , Y02B70/16
摘要： A phase removal control system for a multiphase DC/DC converter including combination logic, disable logic, and a current detector. The multiphase DC/DC converter includes first and second output phase circuits and a controller providing first and second PWM signals for the first and second output phase circuits, respectively. The combination logic combines the second PWM signal with the first PWM signal when a phase enable signal is de-asserted and while a current detect signal indicates current above a predetermined minimum current level. The disable logic passes the second PWM signal to the second output phase circuit when the phase enable signal is asserted and blocks the second PWM signal from the second output phase circuit when the phase enable signal is de-asserted. The current detector has an input for sensing current through the second output phase circuit and an output providing the current detect signal indicative thereof.
摘要翻译：一种用于包括组合逻辑，禁用逻辑和电流检测器的多相DC / DC转换器的去相位控制系统。多相DC / DC转换器包括第一和第二输出相位电路以及分别为第一和第二输出相位电路提供第一和第二PWM信号的控制器。当相位使能信号被解除置位并且当电流检测信号指示高于预定最小电流电平的电流时，组合逻辑将第二PWM信号与第一PWM信号组合。当相位使能信号被置位时，禁止逻辑将第二PWM信号传递到第二输出相位电路，并且当相位使能信号被取消置位时，阻止来自第二输出相位电路的第二PWM信号。电流检测器具有用于感测通过第二输出相位电路的电流的输入和提供指示其的电流检测信号的输出。

4. 发明授权

US07023182B1 Activating a phase in a multiphase DC/DC converter without disturbing the output voltage 失效
标题翻译：激活多相DC / DC转换器中的相位，而不会干扰输出电压
公开(公告)号：US07023182B1
公开(公告)日：2006-04-04
申请号：US11221115
申请日：2005-09-06
申请人： John S. Kleine , Thomas A. Jochum
发明人： John S. Kleine , Thomas A. Jochum
IPC分类号： G05F1/00
CPC分类号： H02M3/1584 , H02M3/157
摘要： A phase activation control system for a multiphase DC/DC converter including an amplifier circuit and enable logic. The converter includes a first phase circuit providing a first PWM signal and has a reduce input for reducing duty cycle of the first PWM signal. The converter further includes a second phase circuit providing a second PWM signal and having an enable input and an increase input for increasing duty cycle of the second PWM signal. The amplifier circuit has an enable input, a current sense input for sensing output current of the converter and an output providing an adjust signal. The adjust signal is provided to the reduce input of the first phase circuit and to the increase input of the second phase circuit. The enable logic receives a phase enable signal and enables the amplifier circuit and the second phase circuit.
摘要翻译：一种用于多相DC / DC转换器的相位激活控制系统，包括放大器电路和使能逻辑。该转换器包括提供第一PWM信号的第一相电路，并具有用于减少第一PWM信号占空比的减小输入。该转换器还包括提供第二PWM信号并具有用于增加第二PWM信号的占空比的使能输入和增加输入的第二相位电路。放大器电路具有使能输入，用于感测转换器的输出电流的电流检测输入和提供调整信号的输出。调整信号被提供给第一相电路的减小输入和第二相电路的增加输入。使能逻辑接收相位使能信号并使能放大器电路和第二相电路。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式