专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US4350537A Semiconductor annealing by pulsed heating 失效
标题翻译：通过脉冲加热进行半导体退火
公开(公告)号：US4350537A
公开(公告)日：1982-09-21
申请号：US195688
申请日：1980-10-09
申请人： John M. Young , Peter D. Scovell
发明人： John M. Young , Peter D. Scovell
IPC分类号： H01L21/265 , H01L21/324 , H01L21/26
CPC分类号： H01L21/26513 , H01L21/324 , Y10S148/09
摘要： A process for annealing crystal damage in ion implanted semiconductor devices in which the device is rapidly heated to a temperature between 450.degree. and 900.degree. C. and allowed to cool. It has been found that such heating of the device to these relatively low temperatures results in rapid annealing. In one application the device (17) may be heated on a graphite element (14) mounted between electrodes (15) in an inert atmosphere in a chamber (11). The process may be enhanced by the application of optical radiation from a Xenon lamp (19).
摘要翻译：一种离子注入半导体器件中退火晶体损伤的方法，其中将器件快速加热至450°至900°C的温度并使其冷却。已经发现，将器件加热到这些相对低的温度导致快速退火。在一个应用中，可以在室（11）中的惰性气氛中的装置（17）上加热安装在电极（15）之间的石墨元件（14）。可以通过施加来自氙灯（19）的光辐射来增强该过程。

2. 发明授权

US4683363A Microwave apparatus for processing semiconductor 失效
标题翻译：微波加工半导体设备
公开(公告)号：US4683363A
公开(公告)日：1987-07-28
申请号：US876306
申请日：1986-06-18
申请人： Peter D. Scovell
发明人： Peter D. Scovell
IPC分类号： H01L21/22 , H01L21/00 , H01L21/324 , H05B6/80
CPC分类号： H01L21/67115 , H01L21/324
摘要： Dopants in semiconductor bodies which have been deactivated during processing are reactivated by pulse heating the body to a temperature within the region in which the semiconductor sheet resistivity decreases with increasing anneal temperature. Typically this comprises raising the body to 1000.degree. C. within 40 seconds or less in an inert atmosphere and allowing it to cool immediately or within approximately 30 seconds. The heating is so rapid that diffusion side effects are minimized. Pulse heating may be achieved by means of a sealable microwave heating chamber (1) which can be pressurized or vented as desired and into which microwave energy is directed for a predetermined time. The microwave heating can also be employed for other processing, particularly high pressure oxidation of silicon. '

3. 发明授权

US4490183A Method of reactivating implanted dopants and oxidation semiconductor wafers by microwaves 失效
标题翻译：通过微波再激活注入的掺杂剂和氧化半导体晶片的方法
公开(公告)号：US4490183A
公开(公告)日：1984-12-25
申请号：US413327
申请日：1982-08-31
申请人： Peter D. Scovell
发明人： Peter D. Scovell
IPC分类号： H01L21/22 , H01L21/00 , H01L21/324 , H01L21/263 , C23C11/00
CPC分类号： H01L21/67115 , H01L21/324
摘要： Dopants in semiconductor bodies which have been deactivated during processing are reactivated by pulse heating the body to a temperature within the region in which the semiconductor sheet resistivity decreases with increasing anneal temperature. Typically this comprises raising the body to 1000.degree. C. within 40 seconds or less in an inert atmosphere and allowing it to cool immediately or within approximately 30 seconds. The heating is so rapid that diffusion side effects are minimized. Pulse heating may be achieved by means of a sealable microwave heating chamber (1) which can be pressurized or vented as desired and into which microwave energy is directed for a predetermined time. The microwave heating can also be employed for other processing, particularly high pressure oxidation of silicon.
摘要翻译：在加工过程中已被去激活的半导体体中的掺杂剂通过将本体脉冲加热到半导体薄层电阻率随着退火温度的升高而降低的区域内的温度而再激活。通常，这包括在惰性气氛中在40秒或更短时间内将物体升高到1000℃，并允许其立即或在约30秒内冷却。加热非常快，扩散副作用最小化。脉冲加热可以通过可密封的微波加热室（1）来实现，该加热室可根据需要加压或排放，微波能量定向到预定时间。微波加热也可用于其他加工，特别是硅的高压氧化。

4. 发明授权

US4965216A Method of fabricating a bi-CMOS device 失效
标题翻译：制造双CMOS器件的方法
公开(公告)号：US4965216A
公开(公告)日：1990-10-23
申请号：US471031
申请日：1990-01-26
申请人： Peter D. Scovell , Peter F. Blomley , Roger L. Baker
发明人： Peter D. Scovell , Peter F. Blomley , Roger L. Baker
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8249 , H01L27/06 , H01L29/08
CPC分类号： H01L29/66272 , H01L21/8249 , H01L27/0623 , H01L29/0804 , Y10S148/123 , Y10S148/124
摘要： A process for fabricating a CMOS compatible bipolar transistor is described. The transistor, which is of the polysilicon emitter type, is fabricated by forming a p-type layer in a well, providing a polysilicon emitter in contact with the layer, using the emitter as a mask to implant p.sup.+ -type base contact regions, and applying contacts to the device.
摘要翻译：描述了制造CMOS兼容双极晶体管的工艺。多晶硅发射体类型的晶体管通过在阱中形成p型层来制造，提供与该层接触的多晶硅发射极，使用发射极作为掩模来注入p +型基极接触区域，以及将联系人应用到设备。

5. 发明授权

US4914048A Method of making Bicmos devices 失效
标题翻译：制造Bicmos设备的方法
公开(公告)号：US4914048A
公开(公告)日：1990-04-03
申请号：US133269
申请日：1987-12-16
申请人： Peter D. Scovell , Peter F. Blomley , Roger L. Baker
发明人： Peter D. Scovell , Peter F. Blomley , Roger L. Baker
IPC分类号： H01L27/092 , H01L21/331 , H01L21/8234 , H01L21/8238 , H01L21/8249 , H01L27/06 , H01L27/088 , H01L29/73 , H01L29/732
CPC分类号： H01L21/8249 , H01L21/8238 , H01L27/0623 , Y10S148/01
摘要： A bipolar transistor structure (1) which can be used in an integrated circuit where bipolar (1) and CMOS transistors (2,3) are formed simultaneously on one substrate. In integrated circuit form the material, for example polycrystalline silicon, used for the gates (11,21) of the CMOS transistors is also used for the emitters (29) of the bipolar transistors, the collectors of the bipolar devices are comprised by doped wells (5) in the substrate (4) and the base contacts of the bipolar devices are comprised by regions (27,27a) equivalent to source and drain regions (17,18) of the n-well MOS transistors and bridged by base implants (28). The conventional CMOS processing is modified by the addition of two masking steps and one implant (base implant). One masking step defines the area for the base implant (18) and the other masking step defines an area of the oxide (30) over the base implant which must be removed to allow contact between the polycrystalline silicon (29), which is suitably doped to provide the emitter, and the base ( 27,27a,28). The base contacts are produced in a semi-self-aligned manner.

6. 发明授权

US4468308A Metallic silicide production 失效
标题翻译：金属硅化物生产
公开(公告)号：US4468308A
公开(公告)日：1984-08-28
申请号：US463375
申请日：1983-02-03
申请人： Peter D. Scovell , Paul J. Rosser , Gary J. Tomkins
发明人： Peter D. Scovell , Paul J. Rosser , Gary J. Tomkins
IPC分类号： C23C26/00 , H01L21/28 , H01L21/324 , C23C15/00
CPC分类号： H01L21/28097 , C23C26/00 , H01L21/324
摘要： A metallic silicide layer is formed on a substrate by pulse heating, in an inert atmosphere, metal and silicon deposited on the substrate to a temperature and for a time sufficient to cause interdiffusion of the metal and silicon.
摘要翻译：金属硅化物层通过在惰性气氛中，在沉积在衬底上的金属和硅的脉冲加热温度和时间足以引起金属和硅的相互扩散而形成在衬底上。

7. 发明授权

US4916517A Semiconductor devices 失效
标题翻译：半导体器件
公开(公告)号：US4916517A
公开(公告)日：1990-04-10
申请号：US282956
申请日：1988-12-05
申请人： Peter D. Scovell , Peter F. Blomley , Roger L. Baker , Gary J. Tomkins
发明人： Peter D. Scovell , Peter F. Blomley , Roger L. Baker , Gary J. Tomkins
IPC分类号： H01L29/73 , H01L21/033 , H01L21/331
CPC分类号： H01L21/0337 , Y10S148/01 , Y10S148/011 , Y10S148/124
摘要： A fully self-aligned polycrystalline silicon emitter bipolar transistor. Self-alignment of the p.sup.+ base contact (12) is achieved by using oxidised sidewalls (8) (sidewall spacers) of the emitter mesa (7) as part of the p.sup.+ base contact implantation mask. Collector contact (13) alignment can be achieved using oxidised sidewalls (17) of polycrystalline silicon alignment mesas (14) defined in the same polysilicon as the emitter mesa (7) but deposited on oxide (2) rather than the implanted base region (5).

8. 发明授权

US4849364A Semiconductor devices 失效
标题翻译：半导体器件
公开(公告)号：US4849364A
公开(公告)日：1989-07-18
申请号：US133270
申请日：1987-12-16
申请人： Peter D. Scovell , Peter F. Blomley , Roger L. Baker
发明人： Peter D. Scovell , Peter F. Blomley , Roger L. Baker
IPC分类号： H01L27/092 , H01L21/331 , H01L21/8234 , H01L21/8238 , H01L21/8249 , H01L27/06 , H01L27/088 , H01L29/73 , H01L29/732
CPC分类号： H01L21/8249 , H01L21/8238 , H01L27/0623 , Y10S148/01
摘要： A method of manufacturing a bipolar transistor (1) with semi-self-aligned p.sup.+ base contacts (27,27a). A p-type base region (28) is formed in a surface region of an n-type region 5 comprising a collector. An element (29) of, for example, n.sup.+ doped polycrystalline silicon, and comprising an emitter, is formed on the surface in contact with the base region (28). The base contacts (27,27a) are formed by implantation and using the element (29) as a mask. An n.sup.+ collector contact (25) is made to the n-tpe region (5).

9. 发明授权

US4772571A Process of self aligned nitridation of TiSi.sub.2 to form TiN/TiSi.sub.2 contact 失效
标题翻译：自对准氮化TiSi2的方法形成TiN / TiSi2接触
公开(公告)号：US4772571A
公开(公告)日：1988-09-20
申请号：US050467
申请日：1987-05-18
申请人： Peter D. Scovell , Paul J. Rosser , Gary J. Tomkins
发明人： Peter D. Scovell , Paul J. Rosser , Gary J. Tomkins
IPC分类号： H01L29/43 , H01L21/28 , H01L21/768 , H01L23/532 , H01L21/283
CPC分类号： H01L21/76886 , H01L21/76889 , H01L23/53257 , H01L2924/0002 , Y10S148/019
摘要： In order to prevent diffusion of silicon from under a titanium disilicide interconnect (1) and into an overlying aluminium layer (6), the disilicide is selectively nitrided by annealing in nitrogen at the points where interconnection between the disilicide and aluminium is required via holes (4) in a silicon dioxide layer (3). The titanium nitrode contacts (5) thus formed in a truly self-aligned manner provide a good barrier to silicon diffusion while having an acceptable low resistivity.
摘要翻译：为了防止硅从二硅化钛互连（1）下方扩散到上覆的铝层（6）中，通过在二硅化物和铝之间的互连需要通孔的点在氮中退火来选择性地氮化二硅化物（ 4）在二氧化硅层（3）中。因此，以真正自对准的方式形成的硝基钛触点（5）为硅扩散提供了良好的屏障，同时具有可接受的低电阻率。

10. 发明授权

US4755487A Method for making bipolar transistors using rapid thermal annealing 失效
标题翻译：使用快速热退火制造双极晶体管的方法
公开(公告)号：US4755487A
公开(公告)日：1988-07-05
申请号：US904547
申请日：1986-09-08
申请人： Peter D. Scovell , Roger L. Baker , David W. McNeil
发明人： Peter D. Scovell , Roger L. Baker , David W. McNeil
IPC分类号： H01L29/73 , H01L21/225 , H01L21/331 , H01L21/324
CPC分类号： H01L21/2256 , Y10S148/09
摘要： In making bipolar transistors, an interfacial oxide layer (5) is formed over ther monocrystalline region (1), and polysilicon (6) is formed both thereon as an extrinsic emitter region. After doping the polysilicon a monocrystalline emitter region (4) is produced in the base region by diffusion from the extrinsic polysilicon emitter region. The oxide layer (5) acts as a diffusion barrier to ensure that excessive dopant does not reach the monocrystalline region.After the above operation, a thermal treatment is effected at a higher temperature, e.g. 1100.degree. C., for a few seconds, which breaks down the interfacial oxide layer referred to above. This temporary use of the interfacial oxide layer leads to better and more consistant transistor characteristics.
摘要翻译：在制造双极晶体管时，在其上的单晶区域（1）上形成界面氧化物层（5），并且在其上形成多晶硅（6）作为外部发射极区域。在掺杂多晶硅之后，通过从非本征多晶硅发射极区域的扩散在基极区域中产生单晶发射极区域（4）。氧化物层（5）用作扩散阻挡层，以确保过量的掺杂剂不会到达单晶区域。在上述操作之后，在更高的温度下进行热处理，例如， 1100℃，几秒钟，这破坏了上述界面氧化物层。这种临时使用界面氧化物层导致更好和更一致的晶体管特性。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式