专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20070245162A1 System and method for blade information handling system power inventory 有权
标题翻译：刀片信息处理系统功率库存的系统和方法
公开(公告)号：US20070245162A1
公开(公告)日：2007-10-18
申请号：US11405967
申请日：2006-04-18
申请人： John Loffink , Michael Brundridge , Mukund Khatri , Timothy Lambert , Pedro Lopez , Jaydev Reddy
发明人： John Loffink , Michael Brundridge , Mukund Khatri , Timothy Lambert , Pedro Lopez , Jaydev Reddy
IPC分类号： G06F1/00
CPC分类号： G06F1/32
摘要： A blade information handling system server prevents excess power demand from blade information handling systems by inventorying the power consumption of each blade information handling system before startup. Another power consumption inventory performed after startup ensures an accurate power consumption inventory for making subsequent startup decision. The baseboard management controller performs the first power consumption inventory with the processing components of the blade information handling system in an off state. The power inventory is communicated to the chassis management controller to obtain authorization to startup based on the power available at the chassis. The second power inventory is performed with the processing components in an on state and forwarded to the chassis management controller for use in subsequent determinations of power available at the chassis.
摘要翻译：刀片信息处理系统服务器通过在启动之前盘点每个刀片信息处理系统的功耗来防止刀片信息处理系统的多余的电力需求。启动后执行的另一个功耗库存确保了准确的功耗库存，以便进行后续的启动决策。基板管理控制器执行第一功耗库存，其中刀片信息处理系统的处理组件处于关闭状态。电源库存通过机箱管理控制器根据机箱可用的功率获得启动授权。第二电力库存在处理组件处于接通状态的情况下被执行，并且被转发到机箱管理控制器，用于随后确定在机架可用的电力。

2. 发明申请

US20070186086A1 Virtual BIOS firmware hub 有权
标题翻译：虚拟BIOS固件集线器
公开(公告)号：US20070186086A1
公开(公告)日：2007-08-09
申请号：US11345818
申请日：2006-02-02
申请人： Timothy Lambert , Stephen Cochran , Mukund Khatri , Pedro Lopez
发明人： Timothy Lambert , Stephen Cochran , Mukund Khatri , Pedro Lopez
IPC分类号： G06F15/177 , G06F9/24
CPC分类号： G06F8/65
摘要： A baseboard management controller (BMC) of a blade server module in an information handling system may operate as a virtual system BIOS firmware hub that may have automatic firmware updating through a TFTP transfer from a chassis management controller (CMC) or for rack/tower servers from a remote assistant card (RMC). The system BIOS may be stored in a RAM drive or a ROM of the BMC. Valuable printed circuit board real estate and hardware for a firmware hub is no longer necessary since the BMC may have the capacity to act as a virtual system BIOS firmware hub in addition to its other functions.
摘要翻译：信息处理系统中的刀片服务器模块的基板管理控制器（BMC）可以作为虚拟系统BIOS固件集线器运行，该固件集线器可以通过来自机箱管理控制器（CMC）或机架/塔式服务器的TFTP传输自动进行固件更新从遥控助理卡（RMC）。系统BIOS可以存储在BMC的RAM驱动器或ROM中。有价值的印刷电路板固件集线器的不动产和硬件不再需要，因为除了其他功能之外，BMC还可能具有充当虚拟系统BIOS固件集线器的能力。

3. 发明申请

US20090070760A1 Virtual Machine (VM) Migration Between Processor Architectures 有权
标题翻译：处理器架构之间的虚拟机（VM）迁移
公开(公告)号：US20090070760A1
公开(公告)日：2009-03-12
申请号：US11850946
申请日：2007-09-06
申请人： Mukund Khatri , Robert Hormuth
发明人： Mukund Khatri , Robert Hormuth
IPC分类号： G06F9/455
CPC分类号： G06F9/5044 , G06F9/45558 , G06F9/4856 , G06F2009/4557
摘要： A system and method for performing a VM migration which manages a cluster of machines in a pool for live migration to the same feature set or behavior. In certain embodiments, machines within the pool can be configured to emulate a certain feature set to enable a VM migration amongst the similar pools. The emulation can be by either masking reporting of a feature set or enabling/disabling a feature set. The handling of emulation registers within the hardware occurs at a firmware level rather than an operating system or hypervisor level.
摘要翻译：用于执行VM迁移的系统和方法，其管理池中的机器集群以便实时迁移到相同的特征集或行为。在某些实施例中，池内的机器可被配置为模拟特定的特征集，以使VM能够在类似的池中迁移。仿真可以通过屏蔽功能集的报告或启用/禁用功能集。硬件中的仿真寄存器的处理发生在固件级别，而不是操作系统或管理程序级别。

4. 发明申请

US20070168585A1 Method and System for Remote Access to Keyboard Control in Legacy USB Mode 有权
标题翻译：远程访问传统USB模式键盘控制的方法和系统
公开(公告)号：US20070168585A1
公开(公告)日：2007-07-19
申请号：US11548436
申请日：2006-10-11
申请人： Austin Bolen , Mukund Khatri , Allen Wynn
发明人： Austin Bolen , Mukund Khatri , Allen Wynn
IPC分类号： G06F13/38
CPC分类号： G06F3/023
摘要： A remote access module associated with a BIOS of an information handling system having a UHCI-based USB controller allows selection of legacy USB control with a local keyboard or access by a remote keyboard through a remote access bus master adapter. Input from an inactive local or remote keyboard results in automated enabling of the inactive keyboard and disabling of the active keyboard. In one embodiment, remote access to a keyboard port during legacy USB control saves the data associated with the remote access to a memory location accessible to the BIOS and invokes the BIOS to obtain the data. In another embodiment, a legacy USB control option is offered by a display to a user associated with a local keyboard and legacy USB control disabled if the user fails to select local access in a predetermined time period.
摘要翻译：与具有基于UHCI的USB控制器的信息处理系统的BIOS相关联的远程访问模块允许使用本地键盘选择传统USB控制或通过远程访问总线主适配器由远程键盘访问。来自不活动的本地或远程键盘的输入导致无效键盘的自动启用和禁用活动键盘。在一个实施例中，在传统USB控制期间远程访问键盘端口将与远程访问相关联的数据保存到BIOS可访问的存储器位置并调用BIOS以获得数据。在另一个实施例中，传统的USB控制选项由显示器提供给与本地键盘相关联的用户，并且如果用户在预定时间段内未能选择本地访问，则传统USB控制被禁用。

5. 发明授权

US09519331B2 Method and apparatus for power throttling of highspeed multi-lane serial links 有权
公开(公告)号：US09519331B2
公开(公告)日：2016-12-13
申请号：US14051612
申请日：2013-10-11
申请人： Mukund Khatri , Lee Zaretsky
发明人： Mukund Khatri , Lee Zaretsky
IPC分类号： G06F1/32
CPC分类号： G06F1/3253 , G06F1/3215 , Y02D10/151
摘要： A method for managing the power consumption of an information handling system including a multi-lane serial link having a lane setting that identifies the number of active lanes in the multi-lane serial link. The method may include determining a number of lanes required for the multi-lane serial link based on one or more I/O devices connected to the information handling system, triggering a reduction of the lane setting of the multi-lane serial link if the lane setting of the multi-lane serial link is greater than the determined number of lanes required, and automatically reducing power to the multi-lane serial link in response to the reduction of the lane setting.

6. 发明申请

US20090307698A1 INFORMATION HANDLING SYSTEM POWER MANAGEMENT DEVICE AND METHODS THEREOF 有权
标题翻译：信息处理系统电源管理装置及其方法
公开(公告)号：US20090307698A1
公开(公告)日：2009-12-10
申请号：US12136518
申请日：2008-06-10
申请人： Mukund Khatri , Vijay Nijhawan , Dirie Herzi , Madhusudhan Rangarajan
发明人： Mukund Khatri , Vijay Nijhawan , Dirie Herzi , Madhusudhan Rangarajan
IPC分类号： G06F9/46
CPC分类号： G06F9/4893 , G06F1/3203 , G06F1/329 , G06F2209/483 , Y02D10/126 , Y02D10/24
摘要： An information handling system includes a set of power and performance profiles. Based on which of the profiles has been selected, the information handling system selects a thread scheduling table for provision to an operating system. The thread scheduling table determines the sequence of processor cores at which program threads are scheduled for execution. In a power-savings mode, the corresponding thread scheduling table provides for threads to be concentrated at subset of available processor cores, increasing the frequency with which the information handling system can place unused processors in a reduced power state.
摘要翻译：信息处理系统包括一组功率和性能特征。基于哪个配置文件被选择，信息处理系统选择线程调度表来提供给操作系统。线程调度表确定程序线程被调度执行的处理器核心的顺序。在省电模式中，对应的线程调度表提供线程集中在可用处理器核心的子集上，从而增加信息处理系统可以将未使用的处理器置于降低功率状态的频率。

7. 发明申请

US20090103444A1 Method and Apparatus for Power Throttling of Highspeed Multi-Lane Serial Links 有权
标题翻译：高速多通道串行链路功率调节方法与装置
公开(公告)号：US20090103444A1
公开(公告)日：2009-04-23
申请号：US11876401
申请日：2007-10-22
申请人： Mukund Khatri , Lee Zaretsky
发明人： Mukund Khatri , Lee Zaretsky
IPC分类号： G06F11/00
CPC分类号： G06F1/3253 , G06F1/3215 , Y02D10/151
摘要： A method for managing the power consumption of an information handling system including a multi-lane serial link having a lane setting that identifies the number of active lanes in the multi-lane serial link. The method may include determining a number of lanes required for the multi-lane serial link based on one or more I/O devices connected to the information handling system, triggering a reduction of the lane setting of the multi-lane serial link if the lane setting of the multi-lane serial link is greater than the determined number of lanes required, and automatically reducing power to the multi-lane serial link in response to the reduction of the lane setting.
摘要翻译：一种用于管理信息处理系统的功耗的方法，所述信息处理系统包括具有标识所述多通道串行链路中的活动通道数目的通道设置的多通道串行链路。该方法可以包括基于连接到信息处理系统的一个或多个I / O设备来确定多通道串行链路所需的车道数量，如果车道行驶则触发减少多车道串行链路的车道设置多车道串行链路的设置大于确定的所需车道数量，并且响应于车道设置的减少而自动降低多车道串行链路的功率。

8. 发明授权

US08874922B2 Systems and methods for multi-layered authentication/verification of trusted platform updates 有权
标题翻译：用于多层认证/可信平台更新验证的系统和方法
公开(公告)号：US08874922B2
公开(公告)日：2014-10-28
申请号：US13351872
申请日：2012-01-17
申请人： Muhammed Jaber , Mukund Khatri
发明人： Muhammed Jaber , Mukund Khatri
IPC分类号： H04L9/32 , G06F21/57
CPC分类号： G06F21/572 , G06F21/57
摘要： In accordance with the present disclosure, a system and method for multilayered authentication of trusted platform updates is described. The method may include storing first cryptographic data in a personality module of an information handling system, with the first cryptographic data corresponding to a verified firmware component. A second cryptographic data may also be determined, with the second cryptographic data corresponding to an unverified firmware component. The unverified firmware component may be stored in a memory element of the information handling system, and the second cryptographic data may be determined using a processor of the information handling system. The method may further include determining if the first cryptographic data matches the second cryptographic data and updating firmware in the information handling system with the unverified firmware component if the first cryptographic data matches the second cryptographic data, and the unverified firmware component includes a digital signature of a manufacturer.
摘要翻译：根据本公开，描述了用于信任平台更新的多层认证的系统和方法。该方法可以包括将第一密码数据存储在信息处理系统的个性模块中，其中第一密码数据对应于已验证的固件组件。还可以确定第二密码数据，其中第二密码数据对应于未验证的固件组件。未验证的固件组件可以存储在信息处理系统的存储器元件中，并且可以使用信息处理系统的处理器来确定第二密码数据。所述方法还可以包括：如果所述第一密码数据与所述第二密码数据匹配，则确定所述第一加密数据是否与所述第二加密数据匹配，以及在所述信息处理系统中更新所述固件，并且所述未验证的固件组件包括：一个制造商。

9. 发明授权

US07882333B2 Architectural enhancements to CPU microcode load mechanism using inter processor interrupt messages 有权
标题翻译：使用中间处理器中断消息对CPU微代码负载机制进行架构性增强
公开(公告)号：US07882333B2
公开(公告)日：2011-02-01
申请号：US11934821
申请日：2007-11-05
申请人： Mukund Khatri
发明人： Mukund Khatri
IPC分类号： G06F15/76 , G06F15/177
CPC分类号： G06F9/4403
摘要： A method for loading microcode to a plurality of cores within a processor. The method includes loading the microcode to a first core of the plurality of cores within the processor system and generating a broadcast inter process interrupt (IPI) message via the first core. The IPI message causes other cores within the processor system to synchronize respective microcode with the microcode that is loaded into the first core. The synchronizing loads microcode to the plurality of cores without requiring independent loads of microcode to each core.
摘要翻译：一种用于将微码加载到处理器内的多个核的方法。该方法包括将微码加载到处理器系统内的多个核心的第一核心，并经由第一核心产生广播中间过程中断（IPI）消息。 IPI消息导致处理器系统内的其他核心将相应的微码与加载到第一核的微码同步。同步将微代码加载到多个核心，而不需要向每个核心独立加载微码。

10. 发明申请

US20080307273A1 System And Method For Predictive Failure Detection 有权
标题翻译：用于预测故障检测的系统和方法
公开(公告)号：US20080307273A1
公开(公告)日：2008-12-11
申请号：US11759088
申请日：2007-06-06
申请人： Tuyet-Huong T. Nguyen , Mukund Khatri
发明人： Tuyet-Huong T. Nguyen , Mukund Khatri
IPC分类号： G06F11/00
CPC分类号： G06F11/0781 , G06F11/073 , G06F11/076 , G06F11/10
摘要： A method of predicting failure of an information handling device, such as a server, by monitoring an error rate, i.e., n errors per error period. Errors are reported only if the error rate is exceeded. An error count is kept, and errors are leaked from the count if the time difference between errors is more than the error period.
摘要翻译：通过监视错误率，即每个错误周期的n个错误来预测诸如服务器的信息处理装置的故障的方法。仅当超过错误率时才报告错误。如果错误之间的时间差大于错误周期，则保留错误计数，错误从计数泄漏。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式