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1. 发明申请

US20070174828A1 Apparatus and method for partitioning programs between a general purpose core and one or more accelerators 有权
标题翻译：用于在通用核心和一个或多个加速器之间划分程序的装置和方法
公开(公告)号：US20070174828A1
公开(公告)日：2007-07-26
申请号：US11339592
申请日：2006-01-25
申请人： John Kevin O'Brien , Kathryn O'Brien , Daniel Prener
发明人： John Kevin O'Brien , Kathryn O'Brien , Daniel Prener
IPC分类号： G06F9/45
CPC分类号： G06F8/45 , G06F8/451 , G06F8/456
摘要： An apparatus and method for partitioning programs between a general purpose core and one or more accelerators are provided. With the apparatus and method, a compiler front end is provided for converting a program source code in a corresponding high level programming language into an intermediate code representation. This intermediate code representation is provided to an interprocedural optimizer which determines which core processor or accelerator each portion of the program should execute on and partitions the program into sub-programs based on this set of decisions. The interprocedural optimizer may further add instructions to the partitions to coordinate and synchronize the sub-programs as required. Each sub-program is compiled on an appropriate compiler backend for the instruction set architecture of the particular core processor or accelerator selected to execute the sub-program. The compiled sub-programs and then linked to thereby generate an executable program.
摘要翻译：提供了用于在通用内核和一个或多个加速器之间分配程序的装置和方法。利用该装置和方法，提供了一种编译器前端，用于将相应高级编程语言中的程序源代码转换为中间代码表示。该中间代码表示被提供给过程间优化器，其确定程序的每个部分应执行哪个核心处理器或加速器，并且基于该组决定将程序分割成子程序。过程间优化器可以进一步向分区添加指令以根据需要协调和同步子程序。每个子程序被编译在用于执行子程序的特定核心处理器或加速器的指令集架构的适当编译器后端上。编译的子程序然后链接从而生成可执行程序。

2. 发明申请

US20060123405A1 Software managed cache optimization system and method for multi-processing systems 失效
标题翻译：用于多处理系统的软件管理缓存优化系统和方法
公开(公告)号：US20060123405A1
公开(公告)日：2006-06-08
申请号：US11002553
申请日：2004-12-02
申请人： John Kevin O'Brien , Kathryn O'Brien
发明人： John Kevin O'Brien , Kathryn O'Brien
IPC分类号： G06F9/45
CPC分类号： G06F8/4442
摘要： The present invention provides for a method for computer program code optimization for a software managed cache in either a uni-processor or a multi-processor system. A single source file comprising a plurality of array references is received. The plurality of array references is analyzed to identify predictable accesses. The plurality of array references is analyzed to identify secondary predictable accesses. One or more of the plurality of array references is aggregated based on identified predictable accesses and identified secondary predictable accesses to generate aggregated references. The single source file is restructured based on the aggregated references to generate restructured code. Prefetch code is inserted in the restructured code based on the aggregated references. Software cache update code is inserted in the restructured code based on the aggregated references. Explicit cache lookup code is inserted for the remaining unpredictable accesses. Calls to a miss handler for misses in the explicit cache lookup code are inserted. A miss handler is included in the generated code for the program. In the miss handler, a line to evict is chosen based on recent usage and predictability. In the miss handler, appropriate DMA commands are issued for the evicted line and the missing line.
摘要翻译：本发明提供了用于在单处理器或多处理器系统中的软件管理高速缓存的计算机程序代码优化的方法。接收包括多个阵列引用的单个源文件。分析多个阵列引用以识别可预测的访问。分析多个阵列引用以识别次级可预测访问。多个阵列引用中的一个或多个基于所识别的可预测访问和识别的次级可预测访问来聚合以生成聚合引用。单个源文件根据聚合引用进行重组，以生成重组代码。预取代码根据聚合引用插入重组的代码中。软件高速缓存更新代码根据聚合引用插入重组的代码中。为其余的不可预测的访问插入了显式缓存查找代码。插入显式缓存查找代码中的未命中处理程序的调用。生成的程序代码中包含一个未命中处理程序。在错误处理程序中，根据最近的使用和可预测性来选择要驱逐的行。在错误处理程序中，针对驱逐行和缺失行发出适当的DMA命令。

3. 发明申请

US20090055588A1 Performing Useful Computations While Waiting for a Line in a System with a Software Implemented Cache 失效
标题翻译：在具有软件实现的缓存的系统中等待线路时执行有用的计算
公开(公告)号：US20090055588A1
公开(公告)日：2009-02-26
申请号：US12243339
申请日：2008-10-01
申请人： John Kevin Patrick O'Brien , Kathryn O'Brien
发明人： John Kevin Patrick O'Brien , Kathryn O'Brien
IPC分类号： G06F12/08
CPC分类号： G06F12/0802 , G06F9/30047 , G06F12/0859
摘要： Mechanisms for performing useful computations during a software cache reload operation are provided. With the illustrative embodiments, in order to perform software caching, a compiler takes original source code, and while compiling the source code, inserts explicit cache lookup instructions into appropriate portions of the source code where cacheable variables are referenced. In addition, the compiler inserts a cache miss handler routine that is used to branch execution of the code to a cache miss handler if the cache lookup instructions result in a cache miss. The cache miss handler, prior to performing a wait operation for waiting for the data to be retrieved from the backing store, branches execution to an independent subroutine identified by a compiler. The independent subroutine is executed while the data is being retrieved from the backing store such that useful work is performed.
摘要翻译：提供了在软件缓存重新加载操作期间执行有用计算的机制。利用说明性实施例，为了执行软件缓存，编译器采用原始源代码，并且在编译源代码的同时，将明确的高速缓存查找指令插入到引用可缓存变量的源代码的适当部分中。另外，如果缓存查找指令导致高速缓存未命中，则编译器插入用于将代码的执行分支到高速缓存未命中处理程序的高速缓存未命中处理程序例程。缓存未命中处理程序在执行等待从后备存储器检索的数据的等待操作之前，将执行分支到编译器识别的独立子程序中。在从后备存储器检索数据时执行独立子程序，从而执行有用的工作。

4. 发明申请

US20080229291A1 Compiler Implemented Software Cache Apparatus and Method in which Non-Aliased Explicitly Fetched Data are Excluded 有权
标题翻译：编译器实现的软件缓存设备和方法，其中排除非别名显式提取的数据
公开(公告)号：US20080229291A1
公开(公告)日：2008-09-18
申请号：US12128194
申请日：2008-05-28
申请人： Tong Chen , John Kevin Patrick O'Brien , Kathryn O'Brien , Byoungro So , Zehra N. Sura , Tao Zhang
发明人： Tong Chen , John Kevin Patrick O'Brien , Kathryn O'Brien , Byoungro So , Zehra N. Sura , Tao Zhang
IPC分类号： G06F9/45
CPC分类号： G06F8/4442
摘要： A compiler implemented software cache apparatus and method in which non-aliased explicitly fetched data are excluded are provided. With the mechanisms of the illustrative embodiments, a compiler uses a forward data flow analysis to prove that there is no alias between the cached data and explicitly fetched data. Explicitly fetched data that has no alias in the cached data are excluded from the software cache. Explicitly fetched data that has aliases in the cached data are allowed to be stored in the software cache. In this way, there is no runtime overhead to maintain the correctness of the two copies of data. Moreover, the number of lines of the software cache that must be protected from eviction is decreased. This leads to a decrease in the amount of computation cycles required by the cache miss handler when evicting cache lines during cache miss handling.
摘要翻译：提供了一种编译器实现的软件缓存装置和方法，其中排除了非别名显式提取的数据。利用说明性实施例的机制，编译器使用前向数据流分析来证明在缓存的数据和显式提取的数据之间没有别名。在缓存数据中没有别名的显式获取的数据将从软件高速缓存中排除。在缓存数据中具有别名的明确获取的数据被允许存储在软件高速缓存中。以这种方式，没有运行时开销来维护两个数据副本的正确性。此外，必须防止驱逐的软件缓存的行数减少。这导致在高速缓存未命中处理期间驱逐高速缓存行时缓存未命中处理程序所需的计算周期量的减少。

5. 发明授权

US07784037B2 Compiler implemented software cache method in which non-aliased explicitly fetched data are excluded 有权
标题翻译：编译器实现软件缓存方法，其中排除非别名显式读取的数据
公开(公告)号：US07784037B2
公开(公告)日：2010-08-24
申请号：US11279768
申请日：2006-04-14
申请人： Tong Chen , John Kevin Patrick O'Brien , Kathryn O'Brien , Byoungro So , Zehra N. Sura , Tao Zhang
发明人： Tong Chen , John Kevin Patrick O'Brien , Kathryn O'Brien , Byoungro So , Zehra N. Sura , Tao Zhang
IPC分类号： G06F9/45
CPC分类号： G06F8/4442
摘要： A compiler implemented software cache is provided in which non-aliased explicitly fetched data are excluded are provided. With the mechanisms of the illustrative embodiments, a compiler uses a forward data flow analysis to prove that there is no alias between the cached data and explicitly fetched data. Explicitly fetched data that has no alias in the cached data are excluded from the software cache. Explicitly fetched data that has aliases in the cached data are allowed to be stored in the software cache. In this way, there is no runtime overhead to maintain the correctness of the two copies of data. Moreover, the number of lines of the software cache that must be protected from eviction is decreased. This leads to a decrease in the amount of computation cycles required by the cache miss handler when evicting cache lines during cache miss handling.
摘要翻译：提供了一种编译器实现的软件高速缓存，其中提供了非别名显式读取的数据。利用说明性实施例的机制，编译器使用前向数据流分析来证明在缓存的数据和显式提取的数据之间没有别名。在缓存数据中没有别名的显式获取的数据将从软件高速缓存中排除。在缓存数据中具有别名的明确获取的数据被允许存储在软件高速缓存中。以这种方式，没有运行时开销来维护两个数据副本的正确性。此外，必须防止驱逐的软件缓存的行数减少。这导致在高速缓存未命中处理期间驱逐高速缓存行时缓存未命中处理程序所需的计算周期量的减少。

6. 发明授权

US07461205B2 Performing useful computations while waiting for a line in a system with a software implemented cache 失效
标题翻译：在使用软件实现的缓存在系统中等待线路时执行有用的计算
公开(公告)号：US07461205B2
公开(公告)日：2008-12-02
申请号：US11421505
申请日：2006-06-01
申请人： John Kevin Patrick O'Brien , Kathryn O'Brien
发明人： John Kevin Patrick O'Brien , Kathryn O'Brien
IPC分类号： G06F12/00 , G06F9/06 , G06F9/30 , G06F9/40
CPC分类号： G06F12/0802 , G06F9/30047 , G06F12/0859
摘要： Mechanisms for performing useful computations during a software cache reload operation are provided. With the illustrative embodiments, in order to perform software caching, a compiler takes original source code, and while compiling the source code, inserts explicit cache lookup instructions into appropriate portions of the source code where cacheable variables are referenced. In addition, the compiler inserts a cache miss handler routine that is used to branch execution of the code to a cache miss handler if the cache lookup instructions result in a cache miss. The cache miss handler, prior to performing a wait operation for waiting for the data to be retrieved from the backing store, branches execution to an independent subroutine identified by a compiler. The independent subroutine is executed while the data is being retrieved from the backing store such that useful work is performed.
摘要翻译：提供了在软件缓存重新加载操作期间执行有用计算的机制。利用说明性实施例，为了执行软件缓存，编译器采用原始源代码，并且在编译源代码的同时，将明确的高速缓存查找指令插入到引用可缓存变量的源代码的适当部分中。另外，如果缓存查找指令导致高速缓存未命中，则编译器插入用于将代码的执行分支到高速缓存未命中处理程序的高速缓存未命中处理程序例程。缓存未命中处理程序在执行等待从后备存储器检索的数据的等待操作之前，将执行分支到编译器识别的独立子程序中。在从后备存储器检索数据时执行独立子程序，从而执行有用的工作。

7. 发明申请

US20070255909A1 SYSTEM AND METHOD FOR GARBAGE COLLECTION IN HETEROGENEOUS MULTIPROCESSOR SYSTEMS 失效
标题翻译：异构多媒体系统中收集的系统和方法
公开(公告)号：US20070255909A1
公开(公告)日：2007-11-01
申请号：US11380683
申请日：2006-04-28
申请人： Michael Gschwind , John O'Brien , Kathryn O'Brien
发明人： Michael Gschwind , John O'Brien , Kathryn O'Brien
IPC分类号： G06F13/00 , G06F12/00
CPC分类号： G06F12/0269 , Y10S707/99953 , Y10S707/99957
摘要： A system and method for garbage collection in heterogeneous multiprocessor systems are provided. In some illustrative embodiments, garbage collection operations are distributed across a plurality of the processors in the heterogeneous multiprocessor system. Portions of a global mark queue are assigned to processors of the heterogeneous multiprocessor system along with corresponding chunks of a shared memory. The processors perform garbage collection on their assigned portions of the global mark queue and corresponding chunk of shared memory marking memory object references as reachable or adding memory object references to a non-local mark stack. The marked memory objects are merged with a global mark stack and memory object references in the non-local mark stack are merged with a “to be traced” portion of the global mark queue for re-checking using a garbage collection operation.
摘要翻译：提供了异构多处理器系统中垃圾收集的系统和方法。在一些说明性实施例中，垃圾收集操作分布在异构多处理器系统中的多个处理器上。全局标记队列的部分被分配给异构多处理器系统的处理器以及共享存储器的对应块。处理器在其分配的全局标记队列的部分上执行垃圾收集，并将相应的共享内存块标记为可访问的内存对象引用，或者向非本地标记堆栈添加内存对象引用。标记的内存对象与全局标记堆栈合并，非本地标记堆栈中的内存对象引用与全局标记队列的“要跟踪”部分合并，以使用垃圾回收操作进行重新检查。

8. 发明申请

US20090070753A1 INCREASE THE COVERAGE OF PROFILING FEEDBACK WITH DATA FLOW ANALYSIS 审中-公开
标题翻译：通过数据流分析增加分布式反馈的覆盖
公开(公告)号：US20090070753A1
公开(公告)日：2009-03-12
申请号：US11851589
申请日：2007-09-07
申请人： Tong Chen , Alexandre E. Eichenberger , Kathryn O'Brien
发明人： Tong Chen , Alexandre E. Eichenberger , Kathryn O'Brien
IPC分类号： G06F9/45
CPC分类号： G06F8/443
摘要： The present invention provides a system and method for profiling based optimization of a computer program. The system includes an optimization module that profiles feedback from profiled part of a program to a part of the program that was not reached, an identical expressions model that identifies at least one identical expression in the program that have not been profiled and copies alias profiling result from a profiled reference to the reference that has not been profiled, a speculative identical expressions model that identifies at least one speculative identical expression in the program that have not been profiled and copies alias profiling result from a profiled speculative identical reference to the speculative identical reference that has not been profiled, and a similar expressions model that identifies at least one similar expression in the program that have not been profiled and copies alias profiling result from a similar profiled reference to the similar reference that has not been profiled.
摘要翻译：本发明提供了一种用于基于计算机程序的轮廓优化的系统和方法。该系统包括一个优化模块，其将从程序的配置文件部分的反馈归因于尚未到达的程序的一部分，相同的表达式模型，其识别程序中至少有一个相同的表达式，该程序中尚未进行概要分析并复制别名分析结果从对未引用的引用的简要引用，一个推测性的相同表达式模型，其标识程序中至少一个没有被分析的猜测相同表达式，并且复制别名分析结果来自于与推测的相同引用的概要相似的引用以及一个类似的表达式模型，用于识别程序中至少有一个类似的表达式，这些表达式尚未被分析，并且复制别名分析结果是从类似的引用引用到尚未被分析的类似引用。

9. 发明申请

US20080282064A1 System and Method for Speculative Thread Assist in a Heterogeneous Processing Environment 有权
标题翻译：异构处理环境中的推理线程辅助系统与方法
公开(公告)号：US20080282064A1
公开(公告)日：2008-11-13
申请号：US11745018
申请日：2007-05-07
申请人： Michael Norman Day , Michael Karl Gschwind , John Kevin Patrick O'Brien , Kathryn O'Brien
发明人： Michael Norman Day , Michael Karl Gschwind , John Kevin Patrick O'Brien , Kathryn O'Brien
IPC分类号： G06F15/00
CPC分类号： G06F9/5044
摘要： A system and method for speculative assistance to a thread in a heterogeneous processing environment is provided. A first set of instructions is identified in a source code representation (e.g., a source code file) that is suitable for speculative execution. The identified set of instructions are analyzed to determine the processing requirements. Based on the analysis, a processor type is identified that will be used to execute the identified first set of instructions based. The processor type is selected from more than one processor types that are included in the heterogeneous processing environment. The heterogeneous processing environment includes more than one heterogeneous processing cores in a single silicon substrate. The various processing cores can utilize different instruction set architectures (ISAs). An object code representation is then generated for the identified first set of instructions with the object code representation being adapted to execute on the determined type of processor.
摘要翻译：提供了一种用于在异构处理环境中对线程进行投机协助的系统和方法。在适于推测性执行的源代码表示（例如，源代码文件）中识别第一组指令。分析所识别的指令集以确定处理要求。基于该分析，识别将用于执行所识别的第一组指令的处理器类型。处理器类型从包含在异构处理环境中的多于一种处理器类型中选择。异质处理环境在单个硅衬底中包括多于一个异质处理核心。各种处理核心可以利用不同的指令集架构（ISA）。然后，针对所识别的第一组指令生成目标代码表示，其中目标代码表示适于在确定类型的处理器上执行。

10. 发明申请

US20080178163A1 Just-In-Time Compilation in a Heterogeneous Processing Environment 审中-公开
标题翻译：异构处理环境中的即时编译
公开(公告)号：US20080178163A1
公开(公告)日：2008-07-24
申请号：US12049286
申请日：2008-03-15
申请人： Michael Karl Gschwind , John Kevin Patrick O'Brien , Kathryn O'Brien
发明人： Michael Karl Gschwind , John Kevin Patrick O'Brien , Kathryn O'Brien
IPC分类号： G06F9/45
CPC分类号： G06F9/45516
摘要： An approach is provided that sends a JIT compilation request from a first process that is running on one processor to a JIT compiler that is running on another processor. The processors are based on different instruction set architectures (ISAs), and share a common memory to transfer data. Non-compiled statements are stored in the shared memory. The JIT compiler reads the non-compiled statements and compiles the statements into executable statements and stores them in the shared memory. The JIT compiler compiles the non-compiled statements destined for the first processor into executable instructions suitable for the first processor and statements destined for another type of processor (based on a different ISA) into instructions suitable for the other processor.
摘要翻译：提供了一种方法，它将JIT编译请求从在一个处理器上运行的第一个进程发送到在另一个处理器上运行的JIT编译器。处理器基于不同的指令集体系结构（ISA），并且共享用于传输数据的公共存储器。非编译语句存储在共享内存中。 JIT编译器读取非编译语句并将语句编译成可执行语句，并将它们存储在共享内存中。 JIT编译器将发往第一个处理器的非编译语句编译成适用于第一个处理器的可执行指令和目的地为另一种类型的处理器（基于不同的ISA）的语句转换为适用于其他处理器的指令。

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