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1. 发明授权

US06448796B1 Selective netlist to test fine pitch multi-chip semiconductor 失效
标题翻译：选择性网表，以测试细间距多芯片半导体
公开(公告)号：US06448796B1
公开(公告)日：2002-09-10
申请号：US09593557
申请日：2000-06-14
申请人： John J. Ellison , Chon C. Lei , Jorge L. Rivera
发明人： John J. Ellison , Chon C. Lei , Jorge L. Rivera
IPC分类号： G01R3102
CPC分类号： G01R31/318513 , G01R31/31926
摘要： A system for testing every one of the signal inputs and outputs (I/O) of a fine pitch multi-chip semiconductor module utilizing a selective netlist, through the intermediary of presently available test equipment. More particularly, the system facilitates the testing of fine pitch multi-chip modules utilizing 1.0 mm ceramic column grid array (CCGA) technology in order to facilitate the use of increased system interconnect capabilities. Additionally, there is provided a method of employing a selective netlist in order to test fine pitch multi-chip semiconductor modules; especially such as, but not limited to 1.0 mm pitch ceramic column grid array (CCGA) modules by employing commercially available test equipment.
摘要翻译：一种用于通过目前可用的测试设备的中介，利用选择性网表来测试每个信号输入和输出（I / O）的细间距多芯片半导体模块的系统。更具体地，该系统便于使用1.0mm陶瓷列网格阵列（CCGA）技术来测试精细间距多芯片模块，以便于使用增加的系统互连能力。此外，提供了一种采用选择性网表以便测试细间距多芯片半导体模块的方法; 特别是例如但不限于采用市售测试设备的1.0mm间距陶瓷柱格栅阵列（CCGA）模块。

2. 发明授权

US6026221A Prototyping multichip module 失效
标题翻译：原型多芯片模块
公开(公告)号：US6026221A
公开(公告)日：2000-02-15
申请号：US25671
申请日：1998-02-18
申请人： John J. Ellison , Dennis Felix Clocher , Joseph John Lisowski , Joseph L. Temple , Michael G. Nealon
发明人： John J. Ellison , Dennis Felix Clocher , Joseph John Lisowski , Joseph L. Temple , Michael G. Nealon
IPC分类号： H01L23/538 , H05K1/00 , H05K1/03 , H05K3/22 , H05K3/28 , G06F1/16 , H01L27/06 , H05K3/40
CPC分类号： H01L23/5382 , H05K1/0287 , H05K1/0292 , H01L2224/16225 , H05K1/0298 , H05K1/0306 , H05K2201/10674 , H05K2203/176 , H05K3/284
摘要： A pre-production, prototype multi-chip module adapted for preliminary performance timing and functional tests includes a plurality of chips attached to a substrate. Multiple nets are embedded within the substrate connecting the chips. A layer over the substrate encapsulates the chips. Production input/output pins on the substrate are connected to the chips. An area on the upper surface of the module is not covered by the encapsulating layer, which contains upper pads adapted for connection of a second module containing spare circuits to the substrate, wherein the upper pads are connected to the at least one net. Some of the upper pads have connections to each other near the surface of the encapsulating layer, wherein the connections are adapted to be severed for connecting a second module containing spare circuits to one or more of the chips.
摘要翻译：适用于初步性能定时和功能测试的预生产原型多芯片模块包括附接到基板的多个芯片。多个网络嵌入在连接芯片的基板内。衬底上的层封装了芯片。基板上的生产输入/输出引脚连接到芯片。模块的上表面上的区域不被封装层覆盖，该封装层包含适于将包含备用电路的第二模块连接到衬底的上焊盘，其中上焊盘连接到至少一个网。一些上焊盘在封装层的表面附近彼此连接，其中连接件适于被切断，用于将包含备用电路的第二模块连接到一个或多个芯片。

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