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1. 发明申请

US20140183753A1 FABRICATING POLYSILICON MOS DEVICES AND PASSIVE ESD DEVICES 有权
标题翻译：制造POLYSILICON MOS器件和被动ESD器件
公开(公告)号：US20140183753A1
公开(公告)日：2014-07-03
申请号：US13733243
申请日：2013-01-03
申请人： John J. Ellis-Monaghan , Michael J. Hauser , Zhong-Xiang He , Junjun Li , Xuefeng Liu , Anthony K. Stamper
发明人： John J. Ellis-Monaghan , Michael J. Hauser , Zhong-Xiang He , Junjun Li , Xuefeng Liu , Anthony K. Stamper
IPC分类号： H01L27/04 , H01L21/36
CPC分类号： B81C1/00301 , B81B7/007 , B81B2207/094 , B81C1/00246 , B81C2203/0714 , B81C2203/0742 , H01L21/84 , H01L27/1203
摘要： A semiconductor fabrication is described, wherein a MOS device and a MEMS device is fabricated simultaneously in the BEOL process. A silicon layer is deposited and etched to form a silicon film for a MOS device and a lower silicon sacrificial film for a MEMS device. A conductive layer is deposited atop the silicon layer and etched to form a metal gate and a first upper electrode. A dielectric layer is deposited atop the conductive layer and vias are formed in the dielectric layer. Another conductive layer is deposited atop the dielectric layer and etched to form a second upper electrode and three metal electrodes for the MOS device. Another silicon layer is deposited atop the other conductive layer and etched to form an upper silicon sacrificial film for the MEMS device. The upper and lower silicon sacrificial films are then removed via venting holes.
摘要翻译：描述了半导体制造，其中在BEOL工艺中同时制造MOS器件和MEMS器件。沉积并蚀刻硅层以形成用于MOS器件的硅膜和用于MEMS器件的下硅牺牲膜。导电层沉积在硅层顶部并被蚀刻以形成金属栅极和第一上电极。介电层沉积在导电层顶上，并且通孔形成在电介质层中。另一个导电层沉积在电介质层顶上并被蚀刻以形成用于MOS器件的第二上电极和三个金属电极。另一硅层沉积在另一导电层的顶上，并被蚀刻以形成用于MEMS器件的上硅牺牲膜。然后通过排气孔去除上部和下部硅牺牲膜。

2. 发明授权

US07915158B2 Method for forming an on-chip high frequency electro-static discharge device 有权
标题翻译：用于形成片上高频静电放电装置的方法
公开(公告)号：US07915158B2
公开(公告)日：2011-03-29
申请号：US12144071
申请日：2008-06-23
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu , Anthony K. Stamper
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu , Anthony K. Stamper
IPC分类号： H01L21/4763
CPC分类号： H01L21/7682 , H01L21/3148 , H01L21/318 , H01L21/3185 , H01L27/0248
摘要： A method for forming an on-chip high frequency electro-static discharge device is described. In one embodiment, a wafer with a multi-metal level wiring is provided. The wafer includes a first dielectric layer with more than one electrode formed therein, a second dielectric layer disposed over the first dielectric layer with more than one electrode formed therein and more than one via connecting the more than one electrode in the first dielectric layer to a respective more than one electrode in the second dielectric layer. The more than one via is misaligned a predetermined amount with the more than one electrodes in the first dielectric layer and the second dielectric layer. The at least one of the misaligned vias forms a narrow gap with another misaligned via. A cavity trench is formed through the second dielectric layer between the narrow gap that separates the misaligned vias.
摘要翻译：描述形成片上高频静电放电装置的方法。在一个实施例中，提供具有多金属层布线的晶片。该晶片包括：第一电介质层，其中形成有多于一个电极;第二电介质层，设置在第一电介质层上，其中形成有多于一个电极，多个通孔将第一介电层中的多于一个的电极连接到在第二介电层中分别有一个以上的电极。多于一个通孔与第一介电层和第二介电层中的多于一个的电极不对准预定量。至少一个不对齐的通孔与另一个不对齐的通孔形成了狭窄的间隙。在分隔未对准的通孔的窄间隙之间通过第二介电层形成腔沟槽。

3. 发明申请

US20090316313A1 DESIGN STRUCTURE FOR AN ON-CHIP HIGH FREQUENCY ELECTRO-STATIC DISCHARGE DEVICE 失效
标题翻译：片上高频电子放电装置的设计结构
公开(公告)号：US20090316313A1
公开(公告)日：2009-12-24
申请号：US12144084
申请日：2008-06-23
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu , Anthony K. Stamper
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu , Anthony K. Stamper
IPC分类号： H02H9/00 , G06F17/50
CPC分类号： G06F17/5068 , H01L23/60 , H01L2924/0002 , H01L2924/00
摘要： A design structure for an on-chip high frequency electro-static discharge device is described. In one embodiment, the electro-static discharge device comprises a substrate and multiple metal level layers disposed on the substrate. Each metal level comprises more than one electrode formed therein and more than one via connecting with some of the electrodes in adjacent metal levels. The device further includes a gap formed about one of the metal level layers, wherein the gap is hermetically sealed to provide electro-static discharge protection for the integrated circuit.
摘要翻译：描述了片上高频静电放电装置的设计结构。在一个实施例中，静电放电装置包括衬底和设置在衬底上的多个金属层。每个金属层包括多于一个电极，其中形成有多个电极，并且多个通孔与相邻金属层中的一些电极连接。所述装置还包括围绕所述金属层之一形成的间隙，其中所述间隙被气密密封以为所述集成电路提供静电放电保护。

4. 发明授权

US07768762B2 Design structure for an on-chip high frequency electro-static discharge device 失效
标题翻译：片上高频静电放电装置的设计结构
公开(公告)号：US07768762B2
公开(公告)日：2010-08-03
申请号：US12144084
申请日：2008-06-23
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu , Anthony K. Stamper
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu , Anthony K. Stamper
IPC分类号： H02H7/20 , H02H9/00
CPC分类号： G06F17/5068 , H01L23/60 , H01L2924/0002 , H01L2924/00
摘要： A design structure for an on-chip high frequency electro-static discharge device is described. In one embodiment, the electro-static discharge device comprises a substrate and multiple metal level layers disposed on the substrate. Each metal level comprises more than one electrode formed therein and more than one via connecting with some of the electrodes in adjacent metal levels. The device further includes a gap formed about one of the metal level layers, wherein the gap is hermetically sealed to provide electro-static discharge protection for the integrated circuit.
摘要翻译：描述了片上高频静电放电装置的设计结构。在一个实施例中，静电放电装置包括衬底和设置在衬底上的多个金属层。每个金属层包括多于一个电极，其中形成有多个电极，并且多个通孔与相邻金属层中的一些电极连接。所述装置还包括围绕所述金属层之一形成的间隙，其中所述间隙被气密密封，以为所述集成电路提供静电放电保护。

5. 发明授权

US07759243B2 Method for forming an on-chip high frequency electro-static discharge device 失效
标题翻译：用于形成片上高频静电放电装置的方法
公开(公告)号：US07759243B2
公开(公告)日：2010-07-20
申请号：US12144089
申请日：2008-06-23
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu , Anthony K. Stamper
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu , Anthony K. Stamper
IPC分类号： H01L21/00
CPC分类号： H01L21/76808 , H01L21/7682 , H01L27/0248
摘要： A method for forming an on-chip high frequency electro-static discharge device on an integrated circuit is described. In one embodiment of the method, a capped first dielectric layer with more than one electrode formed therein is provided. A second dielectric layer is deposited over the capped first dielectric layer. A first hard mask dielectric layer is deposited over the second dielectric layer. A cavity trench is formed through the first hard mask dielectric layer and the second dielectric layer to the first dielectric layer, wherein the cavity trench is formed in the first dielectric layer between two adjacent electrodes. At least one via is formed through the second dielectric layer about the cavity trench. A metal trench is formed around each of the at least one via. A release opening is formed over the cavity trench. A third dielectric layer is deposited over the second dielectric layer, wherein the third dielectric layer hermetically seals the release opening to provide electro-static discharge protection.
摘要翻译：描述了在集成电路上形成片上高频静电放电装置的方法。在该方法的一个实施例中，提供了一种其上形成有多于一个电极的封盖的第一电介质层。在封盖的第一介电层上沉积第二介电层。第一硬掩模介电层沉积在第二介电层上。通过第一硬掩模电介质层和第二电介质层形成腔沟槽到第一介电层，其中在两个相邻电极之间的第一电介质层中形成空腔沟槽。至少一个通孔围绕腔沟槽形成穿过第二电介质层。在所述至少一个通孔中的每一个周围形成金属沟槽。在空腔沟槽上形成释放开口。在第二电介质层上沉积第三电介质层，其中第三介电层气密地密封释放开口以提供静电放电保护。

6. 发明申请

US20090317975A1 METHOD FOR FORMING AN 0N-CHIP HIGH FREQUENCY ELECTRO-STATIC DISCHARGE DEVICE 有权
标题翻译：用于形成0N芯片高频电静电放电装置的方法
公开(公告)号：US20090317975A1
公开(公告)日：2009-12-24
申请号：US12144071
申请日：2008-06-23
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu , Anthony K. Stamper
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu , Anthony K. Stamper
IPC分类号： H01L21/311
CPC分类号： H01L21/7682 , H01L21/3148 , H01L21/318 , H01L21/3185 , H01L27/0248
摘要： A method for forming an on-chip high frequency electro-static discharge device is described. In one embodiment, a wafer with a multi-metal level wiring is provided and a hermetically sealed gap is formed therein to provide electro-static discharge protection for an integrated circuit.
摘要翻译：描述形成片上高频静电放电装置的方法。在一个实施例中，提供具有多金属水平布线的晶片，并且在其中形成气密密封的间隙以为集成电路提供静电放电保护。

7. 发明申请

US20090317970A1 METHOD FOR FORMING AN ON-CHIP HIGH FREQUENCY ELECTRO-STATIC DISCHARGE DEVICE 失效
标题翻译：用于形成片上高频电静电放电装置的方法
公开(公告)号：US20090317970A1
公开(公告)日：2009-12-24
申请号：US12144089
申请日：2008-06-23
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu , Anthony K. Stamper
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu , Anthony K. Stamper
IPC分类号： H01L21/4763
CPC分类号： H01L21/76808 , H01L21/7682 , H01L27/0248
摘要： A method for forming an on-chip high frequency electro-static discharge device on an integrated circuit is described. In one embodiment of the method, a capped first dielectric layer with more than one electrode formed therein is provided. A second dielectric layer is deposited over the capped first dielectric layer. A first hard mask dielectric layer is deposited over the second dielectric layer. A cavity trench is formed through the first hard mask dielectric layer and the second dielectric layer to the first dielectric layer, wherein the cavity trench is formed in the first dielectric layer between two adjacent electrodes. At least one via is formed through the second dielectric layer about the cavity trench. A metal trench is formed around each of the at least one via. A release opening is formed over the cavity trench. A third dielectric layer is deposited over the second dielectric layer, wherein the third dielectric layer hermetically seals the release opening to provide electro-static discharge protection.
摘要翻译：描述了在集成电路上形成片上高频静电放电装置的方法。在该方法的一个实施例中，提供了一种其上形成有多于一个电极的封盖的第一电介质层。在封盖的第一介电层上沉积第二介电层。第一硬掩模介电层沉积在第二介电层上。通过第一硬掩模电介质层和第二电介质层形成腔沟槽到第一介电层，其中在两个相邻电极之间的第一电介质层中形成空腔沟槽。至少一个通孔围绕腔沟槽形成穿过第二电介质层。在所述至少一个通孔中的每一个周围形成金属沟槽。在空腔沟槽上形成释放开口。在第二电介质层上沉积第三电介质层，其中第三介电层气密地密封释放开口以提供静电放电保护。

8. 发明申请

US20090316314A1 DESIGN STRUCTURE FOR AN ON-CHIP HIGH FREQUENCY ELECTRO-STATIC DISCHARGE DEVICE 有权
标题翻译：片上高频电子放电装置的设计结构
公开(公告)号：US20090316314A1
公开(公告)日：2009-12-24
申请号：US12144095
申请日：2008-06-23
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu , Anthony K. Stamper
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu , Anthony K. Stamper
IPC分类号： H02H9/00 , G06F17/50
CPC分类号： H01L23/60 , H01L2924/0002 , H01L2924/00
摘要： A design structure for an on-chip high frequency electro-static discharge device is described. In one embodiment, the electro-static discharge structure comprises a first dielectric layer with more than one electrode formed therein. A second dielectric layer with more than one electrode formed therein is located above the first dielectric layer. At least one via connects the more than one electrode in the first dielectric layer with the more than one electrode in the second dielectric layer. A gap is formed through the first dielectric layer and the second dielectric layer, wherein the gap extends between two adjacent electrodes in both the first dielectric layer and the second dielectric layer. A third dielectric layer is disposed over the second dielectric layer, wherein the third dielectric layer hermetically seals the gap to provide electro-static discharge protection on the integrated circuit.
摘要翻译：描述了片上高频静电放电装置的设计结构。在一个实施例中，静电放电结构包括其中形成有多于一个电极的第一电介质层。其中形成有多于一个电极的第二电介质层位于第一介电层的上方。至少一个通孔将第一介电层中的多于一个的电极与第二介电层中的多于一个的电极连接。通过第一电介质层和第二电介质层形成间隙，其中间隙在第一电介质层和第二电介质层中的两个相邻电极之间延伸。第三电介质层设置在第二电介质层上，其中第三介电层气密地密封间隙以在集成电路上提供静电放电保护。

9. 发明授权

US08279572B2 Structure for an on-chip high frequency electro-static discharge device 有权
标题翻译：一种片上高频静电放电装置的结构
公开(公告)号：US08279572B2
公开(公告)日：2012-10-02
申请号：US12144095
申请日：2008-06-23
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu , Anthony K. Stamper
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu , Anthony K. Stamper
IPC分类号： H02H9/02
CPC分类号： H01L23/60 , H01L2924/0002 , H01L2924/00
摘要： A design structure for an on-chip high frequency electro-static discharge device is described. In one embodiment, the electro-static discharge structure comprises a first dielectric layer with more than one electrode formed therein. A second dielectric layer with more than one electrode formed therein is located above the first dielectric layer. At least one via connects the more than one electrode in the first dielectric layer with the more than one electrode in the second dielectric layer. A gap is formed through the first dielectric layer and the second dielectric layer, wherein the gap extends between two adjacent electrodes in both the first dielectric layer and the second dielectric layer. A third dielectric layer is disposed over the second dielectric layer, wherein the third dielectric layer hermetically seals the gap to provide electro-static discharge protection on the integrated circuit.
摘要翻译：描述了片上高频静电放电装置的设计结构。在一个实施例中，静电放电结构包括其中形成有多于一个电极的第一电介质层。其中形成有多于一个电极的第二电介质层位于第一介电层的上方。至少一个通孔将第一介电层中的多于一个的电极与第二介电层中的多于一个的电极连接。通过第一电介质层和第二电介质层形成间隙，其中间隙在第一电介质层和第二电介质层中的两个相邻电极之间延伸。第三电介质层设置在第二电介质层上，其中第三介电层气密地密封间隙以在集成电路上提供静电放电保护。

10. 发明授权

US09059138B2 Heterojunction bipolar transistor with reduced sub-collector length, method of manufacture and design structure 有权
标题翻译：具有减小的集电极长度的异质结双极晶体管，制造方法和设计结构
公开(公告)号：US09059138B2
公开(公告)日：2015-06-16
申请号：US13358180
申请日：2012-01-25
申请人： Renata Camillo-Castillo , Zhong-Xiang He , Jeffrey B. Johnson , Qizhi Liu , Xuefeng Liu
发明人： Renata Camillo-Castillo , Zhong-Xiang He , Jeffrey B. Johnson , Qizhi Liu , Xuefeng Liu
IPC分类号： H01L29/737 , G06F17/50 , H01L21/331 , H01L29/417 , H01L29/66 , H01L29/10
CPC分类号： H01L29/417 , H01L29/1004 , H01L29/66242 , H01L29/7371
摘要： A heterojunction bipolar transistor (HBT) structure, method of manufacturing the same and design structure thereof are provided. The HBT structure includes a semiconductor substrate having a sub-collector region therein. The HBT structure further includes a collector region overlying a portion of the sub-collector region. The HBT structure further includes an intrinsic base layer overlying at least a portion of the collector region. The HBT structure further includes an extrinsic base layer adjacent to and electrically connected to the intrinsic base layer. The HBT structure further includes an isolation region extending vertically between the extrinsic base layer and the sub-collector region. The HBT structure further includes an emitter overlying a portion of the intrinsic base layer. The HBT structure further includes a collector contact electrically connected to the sub-collector region. The collector contact advantageously extends through at least a portion of the extrinsic base layer.
摘要翻译：提供异质结双极晶体管（HBT）结构，其制造方法及其设计结构。 HBT结构包括其中具有亚集电极区域的半导体衬底。 HBT结构还包括覆盖子集电极区域的一部分的集电极区域。 HBT结构还包括覆盖集电极区域的至少一部分的本征基极层。 HBT结构还包括与本征基极层相邻并电连接的外部基极层。 HBT结构还包括在外部基极层和副集电极区之间垂直延伸的隔离区。 HBT结构还包括覆盖本征基极层的一部分的发射极。 HBT结构还包括电连接到子集电极区的集电极触点。收集器触点有利地延伸穿过外部基极层的至少一部分。

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