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1. 发明授权

US06233184B1 Structures for wafer level test and burn-in 失效
标题翻译：晶圆级测试和老化的结构
公开(公告)号：US06233184B1
公开(公告)日：2001-05-15
申请号：US09191954
申请日：1998-11-13
申请人： John E. Barth , Claude L. Bertin , Jeffrey H. Dreibelbis , Wayne F. Ellis , Wayne J. Howell , Erik L. Hedberg , Howard L. Kalter , William R. Tonti , Donald L. Wheater
发明人： John E. Barth , Claude L. Bertin , Jeffrey H. Dreibelbis , Wayne F. Ellis , Wayne J. Howell , Erik L. Hedberg , Howard L. Kalter , William R. Tonti , Donald L. Wheater
IPC分类号： G11C2900
CPC分类号： G01R31/2855 , G01R31/2806 , G01R31/2831 , G01R31/31905 , H01L2224/05624 , H01L2224/13 , H01L2224/45144 , H01L2224/45147 , H01L2924/00014
摘要： Wafer test and burn-in is accomplished with state machine or programmable test engines located on the wafer being tested. Each test engine requires less than 10 connections and each test engine can be connected to a plurality of chips, such as a row or a column of chips on the wafer. Thus, the number of pads of the wafer that must be connected for test is substantially reduced while a large degree of parallel testing is still provided. The test engines also permit on-wafer allocation of redundancy in parallel so that failing chips can be repaired after burn-in is complete. In addition, the programmable test engines can have their code altered so test programs can be modified to account for new information after the wafer has been fabricated. The test engines are used during burn-in to provide high frequency write signals to DRAM arrays that provide a higher effective voltage to the arrays, lowering the time required for burn-in. Connections to the wafer and between test engines and chips are provided along a membrane attached to the wafer. Membrane connectors can be formed or opened after the membrane is connected to the wafer so shorted chips can be disconnected. Preferably the membrane remains on the wafer after test, burn-in and dicing to provide a chip scale package. Thus, the very high cost of TCE matched materials, such as glass ceramic contactors, for wafer burn-in is avoided while providing benefit beyond test and burn-in for packaging.
摘要翻译：晶圆测试和老化是通过位于被测晶片上的状态机或可编程测试引擎完成的。每个测试引擎需要少于10个连接，并且每个测试引擎可以连接到多个芯片，例如晶片上的行或一列芯片。因此，仍然提供必须连接用于测试的晶片的焊盘数量，同时还提供大量的并行测试。测试引擎还允许并行的片上分配冗余，以便在老化完成后可以修复故障的芯片。此外，可编程测试引擎可以对其代码进行更改，因此可以修改测试程序以在晶圆制造之后考虑新的信息。在老化期间使用测试引擎向DRAM阵列提供高频写入信号，为阵列提供更高的有效电压，从而降低老化所需的时间。沿着连接到晶片的膜提供与晶片和测试引擎与芯片之间的连接。膜连接器可以在膜连接到晶片之后形成或打开，因此短路芯片可以断开。优选地，膜在测试之后保留在晶片上，老化和切割以提供芯片级封装。因此，避免了TCE匹配材料（例如玻璃陶瓷接触器）用于晶片老化的非常高的成本，同时提供超出测试和包装封装的优点。

2. 发明授权

US06426904B2 Structures for wafer level test and burn-in 失效
标题翻译：晶圆级测试和老化的结构
公开(公告)号：US06426904B2
公开(公告)日：2002-07-30
申请号：US09803500
申请日：2001-03-09
申请人： John E. Barth , Claude L. Bertin , Jeffrey H. Dreibelbis , Wayne F. Ellis , Wayne J. Howell , Erik L. Hedberg , Howard L. Kalter , William R. Tonti , Donald L. Wheater
发明人： John E. Barth , Claude L. Bertin , Jeffrey H. Dreibelbis , Wayne F. Ellis , Wayne J. Howell , Erik L. Hedberg , Howard L. Kalter , William R. Tonti , Donald L. Wheater
IPC分类号： G11C2900
CPC分类号： G01R31/2855 , G01R31/2806 , G01R31/2831 , G01R31/31905 , H01L2224/05624 , H01L2224/13 , H01L2224/45144 , H01L2224/45147 , H01L2924/00014
摘要： Wafer test and burn-in is accomplished with state machine or programmable test engines located on the wafer being tested. Each test engine requires less than 10 connections and each test engine can be connected to a plurality of chips, such as a row or a column of chips on the wafer. Thus, the number of pads of the wafer that must be connected for test is substantially reduced while a large degree of parallel testing is still provided. The test engines also permit on-wafer allocation of redundancy in parallel so that failing chips can be repaired after burn-in is complete. In addition, the programmable test engines can have their code altered so test programs can be modified to account for new information after the wafer has been fabricated. The test engines are used during burn-in to provide high frequency write signals to DRAM arrays that provide a higher effective voltage to the arrays, lowering the time required for burn-in. Connections to the wafer and between test engines and chips are provided along a membrane attached to the wafer. Membrane connectors can be formed or opened after the membrane is connected to the wafer so shorted chips can be disconnected. Preferably the membrane remains on the wafer after test, burn-in and dicing to provide a chip scale package. Thus, the very high cost of TCE matched materials, such as glass ceramic contactors, for wafer burn-in is avoided while providing benefit beyond test and burn-in for packaging.
摘要翻译：晶圆测试和老化是通过位于被测晶片上的状态机或可编程测试引擎完成的。每个测试引擎需要少于10个连接，并且每个测试引擎可以连接到多个芯片，例如晶片上的行或一列芯片。因此，仍然提供必须连接用于测试的晶片的焊盘数量，同时还提供大量的并行测试。测试引擎还允许并行的片上分配冗余，以便在老化完成后可以修复故障的芯片。此外，可编程测试引擎可以对其代码进行更改，因此可以修改测试程序以在晶圆制造之后考虑新的信息。在老化期间使用测试引擎向DRAM阵列提供高频写入信号，为阵列提供更高的有效电压，从而降低了老化所需的时间。沿着连接到晶片的膜提供与晶片和测试引擎与芯片之间的连接。膜连接器可以在膜连接到晶片之后形成或打开，因此短路芯片可以断开。优选地，膜在测试之后保留在晶片上，老化和切割以提供芯片级封装。因此，避免了TCE匹配材料（例如玻璃陶瓷接触器）用于晶片老化的非常高的成本，同时提供超出测试和包装封装的优点。

3. 发明授权

US6044024A Interactive method for self-adjusted access on embedded DRAM memory macros 失效
标题翻译：嵌入式DRAM内存宏自动调整访问的交互方式
公开(公告)号：US6044024A
公开(公告)日：2000-03-28
申请号：US7433
申请日：1998-01-14
申请人： John E. Barth , Jeffrey H. Dreibelbis , Howard L. Kalter
发明人： John E. Barth , Jeffrey H. Dreibelbis , Howard L. Kalter
IPC分类号： G11C11/417 , G06F12/00 , G11C7/10 , G11C11/401 , G11C11/407 , H01L21/822 , H01L27/04 , G11C16/04 , G11C7/02
CPC分类号： G11C7/10
摘要： An embedded memory macro device includes a memory system and a logic circuit constructed on a common semiconductor substrate. The memory system and logic circuit communicate through a handshake procedure via a system data interlock signal. During read cycles the memory system uses the system data interlock signal to tell the logic circuit when data at memory system data outputs is valid. In the preferred embodiment, during write cycles the memory system uses the system data interlock signal to tell the logic circuit when data has been successfully written. The logic circuit needs to wait only until the system data interlock signal permits it to proceed. It then signals the memory system to reset the system data interlock signal and can immediately initiate a new read or write cycle.
摘要翻译：嵌入式存储器宏器件包括存储器系统和构造在公共半导体衬底上的逻辑电路。存储器系统和逻辑电路经由系统数据互锁信号通过握手程序进行通信。在读周期中，当存储器系统数据输出的数据有效时，存储器系统使用系统数据互锁信号来告知逻辑电路。在优选实施例中，在写入周期期间，当数据被成功写入时，存储器系统使用系统数据互锁信号来告诉逻辑电路。逻辑电路需要等到系统数据互锁信号允许它继续进行。然后，它将信号通知存储系统以复位系统数据互锁信号，并可以立即启动新的读或写周期。

4. 发明申请

US20090144492A1 STRUCTURE FOR IMPLEMENTING DYNAMIC REFRESH PROTOCOLS FOR DRAM BASED CACHE 有权
标题翻译：实施基于DRAM的缓存的动态刷新协议的结构
公开(公告)号：US20090144492A1
公开(公告)日：2009-06-04
申请号：US12126499
申请日：2008-05-23
申请人： John E. Barth , Philip G. Emma , Erik L. Hedberg , Hillery C. Hunter , Peter A. Sandon , Vijayalakshmi Srinivasan , Arnold S. Tran
发明人： John E. Barth , Philip G. Emma , Erik L. Hedberg , Hillery C. Hunter , Peter A. Sandon , Vijayalakshmi Srinivasan , Arnold S. Tran
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0893 , G06F2212/304 , Y02D10/13
摘要： A hardware description language (HDL) design structure embodied on a machine-readable data storage medium includes elements that when processed in a computer aided design system generates a machine executable representation of a device for implementing dynamic refresh protocols for DRAM based cache. The HDL design structure further includes a DRAM cache partitioned into a refreshable portion and a non-refreshable portion; and a cache controller configured to assign incoming individual cache lines to one of the refreshable portion and the non-refreshable portion of the cache based on a usage history of the cache lines; wherein cache lines corresponding to data having a usage history below a defined frequency are assigned by the controller to the refreshable portion of the cache, and cache lines corresponding to data having a usage history at or above the defined frequency are assigned to the non-refreshable portion of the cache.
摘要翻译：体现在机器可读数据存储介质上的硬件描述语言（HDL）设计结构包括当在计算机辅助设计系统中处理时生成用于实现基于DRAM的高速缓存的动态刷新协议的设备的机器可执行表示的元件。 HDL设计结构还包括划分为可刷新部分和不可刷新部分的DRAM高速缓存; 以及高速缓存控制器，被配置为基于所述高速缓存行的使用历史将输入的各个高速缓存行分配给所述高速缓存的可刷新部分和不可刷新部分之一; 其中对应于具有低于定义频率的使用历史的数据的高速缓存行被控制器分配给高速缓存的可刷新部分，并且与具有等于或高于定义频率的使用历史的数据相对应的高速缓存行被分配给不可刷新部分缓存。

5. 发明申请

US20080270683A1 SYSTEMS AND METHODS FOR A DRAM CONCURRENT REFRESH ENGINE WITH PROCESSOR INTERFACE 审中-公开
标题翻译：具有处理器接口的DRAM同时燃烧发动机的系统和方法
公开(公告)号：US20080270683A1
公开(公告)日：2008-10-30
申请号：US11739899
申请日：2007-04-25
申请人： John E. Barth , Richard E. Matick , Stanley E. Schuster
发明人： John E. Barth , Richard E. Matick , Stanley E. Schuster
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： Systems and methods for a DRAM concurrent refresh engine with processor interface. In exemplary embodiments, memory cells requiring periodic refresh at least once each for a specified refresh interval and words of an array organized banks in which the banks are selected for access by a bank-enable signal, each bank having a word decoder accepting one of two refresh word addresses, one refresh word address for a normal access, and the other for a refresh access, one of the word addresses selected by two separate enable signals, provided by on-macro refresh logic, which includes instructions to select one bank for refresh when no normal access occurs and select one bank for refresh concurrently with a normal access having no bank conflicts, the refresh logic maintaining the refresh status, timing of the refresh interval, and insuring all memory cells are refreshed within the refresh interval.
摘要翻译：具有处理器接口的DRAM并发刷新引擎的系统和方法。在示例性实施例中，需要对于指定的刷新间隔至少每次刷新一次的存储器单元以及阵列组合的存储体的组，其中通过存储体使能信号选择存储体以进行存取，每个存储体具有接受两个刷新字地址，用于正常访问的一个刷新字地址，另一个用于刷新访问，由宏宏刷新逻辑提供的由两个单独使能信号选择的字地址之一，其包括选择一个银行刷新的指令当没有正常访问时，并且在没有存在冲突的正常访问的情况下同时选择一个存储体进行刷新，保持刷新状态的刷新逻辑，刷新间隔的定时以及保证所有存储单元在刷新间隔内被刷新。

6. 发明授权

US06845059B1 High performance gain cell architecture 失效
标题翻译：高性能增益单元架构
公开(公告)号：US06845059B1
公开(公告)日：2005-01-18
申请号：US10604109
申请日：2003-06-26
申请人： Matthew R. Wordeman , John E. Barth , Toshiaki Kirihata
发明人： Matthew R. Wordeman , John E. Barth , Toshiaki Kirihata
IPC分类号： G11C7/10 , G11C8/16 , G11C11/406 , G11C11/4096 , G11C8/00
CPC分类号： G11C8/16 , G11C7/106 , G11C7/1087 , G11C11/40603 , G11C11/40615
摘要： A memory architecture that utilizes single-ended dual-port destructive write memory cells and a local write-back buffer is described. Each cell has separate read and write ports that make it possible to read-out data from cells on one wordline in the array, and subsequently write-back to those cells while simultaneously reading-out the cell on another wordline in the array. By implementing an array of sense amplifiers such that one amplifier is coupled to each read bitline, and a latch receiving the result of the sensed data and delivering this data to the write data lines, it is possible to ‘pipeline’ the read-out and write-back phases of the read cycle. This allows for a write-back phase from one cycle to occur simultaneously with the read-out phase of another cycle. By extending the operation of the latch to accept data either from the sense amplifier, or from the memory data inputs, modified by the column address and masking bits, it is also possible to pipeline the read-out and the modify-write-back phases of a write cycle, allowing them to occur simultaneously. The architecture preferably employs a nondestructive read memory cell such as 2T or 3T gain cells, achieving an SRAM-like cycle and access times with a smaller and more SER immune memory cell.
摘要翻译：描述了利用单端双端口破坏性写存储器单元和本地回写缓冲器的存储架构。每个单元都具有单独的读取和写入端口，可以从阵列中的一个字线上的单元读出数据，随后将其写回到这些单元格，同时读出数组中另一个字线上的单元格。通过实现读出放大器的阵列，使得一个放大器耦合到每个读取位线，以及一个接收感测数据的结果并将该数据传送到写入数据线的锁存器，可以“管理”读出和读周期的回写阶段。这允许来自一个周期的回写阶段与另一个周期的读出阶段同时发生。通过扩展锁存器的操作以接受来自读出放大器或由存储器数据输入的数据，由列地址和掩码位修改，还可以管理读出和修改回写阶段的写周期，允许它们同时发生。该架构优选采用非破坏性读取存储器单元，例如2T或3T增益单元，通过较小和更多的SER免疫存储单元实现SRAM类周期和访问时间。

7. 发明授权

US08108609B2 Structure for implementing dynamic refresh protocols for DRAM based cache 有权
标题翻译：用于实现基于DRAM的缓存的动态刷新协议的结构
公开(公告)号：US08108609B2
公开(公告)日：2012-01-31
申请号：US12126499
申请日：2008-05-23
申请人： John E. Barth , Philip G. Emma , Erik L. Hedberg , Hillery C. Hunter , Peter A. Sandon , Vijayalakshmi Srinivasan , Arnold S. Tran
发明人： John E. Barth , Philip G. Emma , Erik L. Hedberg , Hillery C. Hunter , Peter A. Sandon , Vijayalakshmi Srinivasan , Arnold S. Tran
IPC分类号： G06F12/00
CPC分类号： G06F12/0893 , G06F2212/304 , Y02D10/13
摘要： A hardware description language (HDL) design structure embodied on a machine-readable data storage medium includes elements that when processed in a computer aided design system generates a machine executable representation of a device for implementing dynamic refresh protocols for DRAM based cache. The HDL design structure further includes a DRAM cache partitioned into a refreshable portion and a non-refreshable portion; and a cache controller configured to assign incoming individual cache lines to one of the refreshable portion and the non-refreshable portion of the cache based on a usage history of the cache lines; wherein cache lines corresponding to data having a usage history below a defined frequency are assigned by the controller to the refreshable portion of the cache, and cache lines corresponding to data having a usage history at or above the defined frequency are assigned to the non-refreshable portion of the cache.
摘要翻译：体现在机器可读数据存储介质上的硬件描述语言（HDL）设计结构包括当在计算机辅助设计系统中处理时生成用于实现基于DRAM的高速缓存的动态刷新协议的设备的机器可执行表示的元件。 HDL设计结构还包括划分为可刷新部分和不可刷新部分的DRAM高速缓存; 以及高速缓存控制器，被配置为基于所述高速缓存行的使用历史将输入的各个高速缓存行分配给所述高速缓存的可刷新部分和不可刷新部分之一; 其中对应于具有低于定义频率的使用历史的数据的高速缓存行被控制器分配给高速缓存的可刷新部分，并且与具有等于或高于定义频率的使用历史的数据相对应的高速缓存行被分配给不可刷新部分缓存。

8. 发明申请

US20070297264A1 MEMORY CELL ACCESS CIRCUIT 有权
标题翻译：存储单元访问电路
公开(公告)号：US20070297264A1
公开(公告)日：2007-12-27
申请号：US11426102
申请日：2006-06-23
申请人： John E. Barth
发明人： John E. Barth
IPC分类号： G11C7/02 , G11C7/00 , G11C8/00
CPC分类号： G11C7/18 , G11C7/1051 , G11C11/4091 , G11C11/4093 , G11C11/4097
摘要： A circuit for accessing a memory cell includes a local bitline and a local sense amplifier having a plurality of transistors. The local bitline may be connect the memory cell and the sense amplifier. A first global bitline may be connected to a first one of the plurality of transistors. A second global bitline may be connected to a second one of the plurality of transistors. A secondary sense amplifier may be connected to the first and second global bitlines.
摘要翻译：用于访问存储器单元的电路包括本地位线和具有多个晶体管的本地读出放大器。本地位线可以连接存储单元和读出放大器。第一全局位线可以连接到多个晶体管中的第一个。第二全局位线可以连接到多个晶体管中的第二全局位线。次级读出放大器可以连接到第一和第二全局位线。

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